HC4GX15 Datasheet, PDF (569/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Description of Transceiver Channel Reconfiguration Modes
2–111
1 The values at logical_tx_pll_sel and logical_tx_pll_sel_en
need to be held at a constant logic level until the
channel_reconfig_done signal is asserted.
Table 2–30 shows how the dynamic reconfiguration controller selects between the
logical reference index stored in the .mif (logical tx pll) and the logical reference
index specified at the logical_tx_pll_sel port.
Table 2–30. Various Combinations of the logical_tx_pll_sel and logical_tx_pll_sel_en Ports
logical_tx_pll_sel
enabled
enabled
enabled
enabled
logical_tx_pll_sel_en
enabled and value is 1
enabled and value is 0
disabled
disabled
Logical Reference Index Value Selected
by the ALTGX_RECONFIG Instance
Value on the logical_tx_pll_sel
port
logical reference index value stored in the
.mif (logical tx pll)
Value on the logical_tx_pll_sel
port
logical reference index value stored in the
.mif (logical tx pll)
When you configure a transceiver channel in the ALTGX MegaWizard Plug-In
Manager, Altera recommends that you keep track of the transmitter PLL that
drives the channel.
1 The logical_tx_pll_sel port does not modify transceiver settings on
the RX side.
© June 2009 Altera Corporation
HardCopy IV Device Handbook, Volume 3