HC4GX15 Datasheet, PDF (306/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–42
Chapter 1: HardCopy IV GX Transceiver Architecture
Transmitter Channel Datapath
Figure 1–27. Control Word and Data Word Transmission
clock
tx_datain[7:0]
83
78
BC
BC
0F
00
BF
3C
tx_ctrlenable
code group
D3.4 D24.3
D28.5
K28.5 D15.0
D0.0
D31.5
D28.1
The IEEE 802.3 8B/10B encoder specification identifies only a set of 8-bit characters
for which tx_ctrlenable should be asserted. If you assert tx_ctrlenable for
any other set of bytes, the 8B/10B encoder might encode the output 10-bit code as an
invalid code (it does not map to a valid Dx.y or Kx.y code), or unintended valid Dx.y
code, depending on the value entered. It is possible for a downstream 8B/10B decoder
to decode an invalid control word into a valid Dx.y code without asserting code error
flags.
1 For example, depending on the current running disparity, the invalid code K24.1
(tx_datain = 8'h38 + tx_ctrl = 1'b1) can be encoded to 10'b0110001100 (0 × 18C),
which is equivalent to a D24.6+ (8'hD8 from the RD+ column). Altera recommends
that you do not assert tx_ctrlenable for unsupported 8-bit characters.
Reset Condition
The tx_digitalreset signal resets the 8B/10B encoder. During reset, running
disparity and data registers are cleared. Also, the 8B/10B encoder outputs a K28.5
pattern from the RD- column continuously until tx_digitalreset is de-asserted.
The input data and control code from the core fabric is ignored during the reset state.
Once out of reset, the 8B/10B encoder starts with a negative disparity (RD-) and
transmits three K28.5 code groups for synchronization before it starts encoding and
transmitting the data on its output.
1 While tx_digitalreset is asserted, the downstream 8B/10B decoder that receives
the data might observe synchronization or disparity errors.
Figure 1–28 shows the reset behavior of the 8B/10B encoder. When in reset
(tx_digitalreset is high), a K28.5 (K28.5 10-bit code group from the RD-column)
is sent continuously until tx_digitalreset is low. Due to some pipelining of the
transmitter channel PCS, some “don’t cares” (10'hxxx) are sent before the three
synchronizing K28.5 code groups. User data follows the third K28.5 code group.
Figure 1–28. 8B/10B Encoder Output During tx_digitalreset Assertion
clock
tx_digitalreset
dataout[9:0] K28.5- K28.5- K28.5- xxx
...
xxx
K28.5- K28.5+ K28.5- Dx.y+
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation