HC4GX15 Datasheet, PDF (596/668 Pages) Altera Corporation – HardCopy IV Device Handbook

2–138
Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Design Examples: Dynamic Reconfiguration Controller
Section III—Logic and Clocking for the GIGE and SONET/SDH OC48 Datapath
In the ALTGX MegaWizard Plug-In Manager, the channel interface that created
tx_datainfull[43:0] and rx_dataoutfull[63:0] was selected. In addition,
the rx_byteorderalignstatus and rx_a1a2size signals were selected. The core
fabric selectively uses some of these signals based on whether the transceiver channel
is configured in a GIGE configuration or a SONET/SDH OC48 configuration.
Table 2–39 provides descriptions for the tx_datainfull[43:0] and
rx_dataoutfull[63:0] signals for GIGE and SONET/SDH OC48 configurations.
Table 2–39. Core Fabric-Transceiver Interface Signals—GIGE and SONET/SDH OC48 Configurations
SIgnal Name
Description
GIGE Configuration
tx_datainfull[7:0] 8-bit unencoded data input to the transceiver channel
tx_datainfull[8]
tx_ctrlenable (control signal K/D)
rx_dataoutfull[7:0] 8-bit unencoded data output from the transceiver channel
rx_dataoutfull[8]
rx_ctrldetect (control signal K/D)
rx_dataoutfull[9]
rx_errdetect
rx_dataoutfull[10] rx_syncstatus
rx_dataoutfull[11] rx_disperr
rx_dataoutfull[12] rx_patterndetect
SONET/SDH OC48 Configuration
tx_datainfull[7:0] LSB data input to the transceiver channel
tx_datainfull[29:22] MSB data input to the transceiver channel
rx_dataoutfull[7:0] LSB data output from the transceiver channel
rx_dataoutfull[29:22 MSB data output from the transceiver channel
rx_dataoutfull[10],
rx_dataoutfull[42]
rx_syncstatus[1:0]
rx_dataoutfull[12],
rx_dataoutfull[44]
rx_patterndetect[1:0]
Clocking
For the transmit side, the core fabric user logic for the SONET/SDH OC48 and GIGE
configurations sends the data synchronized to the tx_clkout signal. Therefore, the
clocking for the transmit side remains the same for the two modes.
For the receive side, the data and status signals from the ALTGX instance for the GIGE
configuration is synchronized to tx_clkout because rate matching is used. For the
SONET/SDH OC48 configuration, the signals are synchronized to rx_clkout.
Therefore, the core fabric user logic has two functional protocol specific logic blocks to
handle data for the GIGE and SONET/SDH OC48 configurations. Based on the
configured protocol mode, the receive side logic selects the appropriate data path.
HardCopy IV Device Handbook, Volume 3
© June 2009 Altera Corporation