HC4GX15 Datasheet, PDF (522/668 Pages) Altera Corporation – HardCopy IV Device Handbook

2–64
Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Description of Transceiver Channel Reconfiguration Modes
Blocks Reconfigured in the Data Rate Division in TX Mode
The only block that is reconfigured by this mode is the TX local divider block of a
transmitter channel. The TX local divider can be set to a divide by value of /1, /2, or
/4, as shown in Figure 2–28.
Figure 2–28. Local Divider of a Transmitter Channel
High-Speed clock
from TX PLL0
High-Speed clock
from TX PLL1
/n
/1, /2, or /4
/4, /5, /8, or /10
High-Speed Serial Clock
Low-Speed Parallel Clock
You must be aware of the device operating range before you enable and use this
feature. There are no legal checks that are imposed by the Quartus II software because
it is an on-the-fly control feature. You also need to ensure that a specific functional
mode supports the data rate range before dividing the clock when using this rate
switch option.
1 The Date Rate Division in TX mode is applicable only to regular transceiver channels
and not the PMA-only channels.
ALTGX MegaWizard Plug-In Manager Setup
Enable the following settings in the ALTGX MegaWizard Plug-In Manager:
1. Select the Channel and Transmitter PLL Reconfiguration option in the Reconfig
screen to enable the ALTGX_RECONFIG instance to modify the TX channel local
divider values dynamically.
2. Set the What is the starting channel number? option in the Reconfig screen. For
more information, refer to “Logical Channel Addressing” on page 2–23.
The alternate reference clock is not required because a single clock source is used. The
/1, /2, or /4 data rates can be derived from the single input reference clock.
HardCopy IV Device Handbook, Volume 3
© June 2009 Altera Corporation