HC4GX15 Datasheet, PDF (298/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–34
Chapter 1: HardCopy IV GX Transceiver Architecture
Transceiver Channel Architecture
ATX Clock Divider
The ATX clock divider divides the ATX PLL high-speed clock and provides
high-speed serial and low-speed parallel clock for bonded functional modes such as
PCI Express (PIPE) (×4, ×8), Basic ×4 and ×8, and PMA-Direct mode with ×N
configuration. For PIPE functional mode support, the ATX clock divider consists of
the PIPE rateswitch circuit to enable dynamic rateswitch between PIPE Gen1 and
Gen2 data rates. For more information about this circuit, refer to “CMU0 Channel” on
page 1–24.
The clock outputs from the ATX PLL block are provided to the transmitter channels
through the ×N_Top or ×N_bottom clock lines, as shown in Figure 1–18.
Figure 1–18. ATX Clock Divider
PCIE_gen2switch_done
PCIE_gen2switch
ATX PLL
high-speed
clock output
ATX clock divider block
PCI Express
clockswitch circuit
0
/S
(4, 5, 8, 10)
/2
1
Low-Speed
Parallel Clocks
(for bonded modes)
coreclkout to core fabric
(for bonded modes)
High-Speed
Serial Clock
(for bonded modes)
Transceiver Channel Architecture
Figure 1–19 shows the HardCopy IV GX transceiver channel datapath.
Figure 1–19. HardCopy IV Transceiver Datapath
TX Phase
Compensation
FIFO
Byte
Serializer
8B/10B
Encoder
Transmitter Channel PCS ^{Transmitter Channel}
PMA
Serializer
tx_dataout
Core
Fabric
PCI
Express
hardIP
PIPE
Interface
RX
Phase
Compensation
FIFO
Byte
Ordering
Byte
De-
serializer
8B/10
Decoder
Receiver Channel PCS
Receiver Channel
PMA
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
De-
Serializer
CDR
rx_datain
Each transceiver channel consists of the following:
■ Transmitter channel, further divided into
■ Transmitter channel PCS
■ Transmitter channel PMA
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation