HC4GX15 Datasheet, PDF (661/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: DC and Switching Characteristics of HardCopy IV Devices
1–31
I/O Timing Model
Table 1–36. HardCopy IV DLL Frequency Range Specifications—Preliminary (Note 1)
Frequency
Mode
Frequency Range
(MHz)
Available Phase Shift
DQS Delay Buffer Mode Number of Delay
(2)
Chains
0
90-140
45°, 90°, 135°, 180°
Low
16
1
120-190
30°, 60, 90°, 120°
Low
12
2
150-230
36°, 72°, 108°, 144°
Low
10
3
180-290
45°, 90°, 135°, 180°
Low
8
4
240-350
30°, 60, 90°, 120°
High
12
5
290-420
36°, 72°, 108°, 144°
High
10
6
360-540 (3)
45°, 90°, 135°, 180°
High
8
Note to Table 1–36:
(1) Pending silicon characterization
(2) Low indicates 6-bit DQS delay setting, high indicates 5-bit DQS delay setting.
(3) Frequency > 530 MHz on Mode 6 is to for 533 MHz DDR3 support. Pending IP support. Actual achievable performance is based on design and
system-specific factors. For DDR3 > 400 MHz, please contact Altera.
OCT Calibration Block Specifications
Table 1–37 describes the OCT calibration block specifications for HardCopy IV
devices.
Table 1–37. OCT Calibration Block Specifications—Preliminary
Symbol
Description
Min Typ Max Unit
OCTUSRCLK Clock required by OCT calibration blocks
— — 20 MHz
TO C T CAL
TO C T SH I FT
Number of OCTUSRCLK clock cycles required for OCT R_S/R_T calibration — 1000 — Cycles
Number of OCTUSRCLK clock cycles required for OCT code to shift out — 28 — Cycles
TR S _ RT
Time required to dynamically switch from R_S to R_T
— 2.5 — ns
Duty Cycle Distortion (DCD) Specifications
Table 1–38 lists the worst case DCD for HardCopy IV devices.
Table 1–38. DCD on HardCopy IV I/O Pins—Preliminary
Symbol
Min
Max
Unit
Output Duty Cycle
45
55
%
I/O Timing Model
The I/O timing specifications for HardCopy IV devices will be available in a future
revision of this chapter.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 4