HC4GX15 Datasheet, PDF (120/668 Pages) Altera Corporation – HardCopy IV Device Handbook

8–10
Chapter 8: High-Speed Differential I/O Interfaces and DPA in HardCopy IV Devices
Soft-CDR Mode
Figure 8–9. DPA Clock Phase to Serial Data Timing Relationship
rx_in
0˚
45˚
D0
D1
D2
D3
D4
Dn
90˚
135˚
180˚
225˚
270˚
315˚
0.125T_vco
T_vco
The DPA block continuously monitors the phase of the incoming serial data and
selects a new clock phase if required. You can prevent the DPA from selecting a new
clock phase by asserting the optional rx_dpll_hold port, which is available for each
channel.
The DPA block requires a training pattern and a training sequence of at least 256
repetitions. The training pattern is not fixed, so you can use any training pattern with
at least one transition on each channel. An optional output port (rx_dpa_locked) is
available to the internal logic to indicate when the DPA block has settled on the closest
phase to the incoming data phase. The DPA block de-asserts rx_dpa_locked
depending on the option selected in the Quartus II MegaWizard Plug-In Manager,
when either a new phase is selected, or when the DPA has moved two phases in the
same direction. The rx_dpa_locked signal is synchronized to the DPA clock domain
and should be considered as the initial indicator for the lock condition. Use data
checkers to validate the data integrity.
An independent reset port (rx_reset) is available to reset the DPA circuitry. The
DPA circuitry must be retrained after reset.
Soft-CDR Mode
The HardCopy IV LVDS channel offers soft-CDR mode to support the Gigabit
Ethernet/SGMII protocols. Clock-data recovery (CDR) is required to extract the clock
out of the clock-embedded data to support SGMII. In HardCopy IV devices, the CDR
circuit is implemented in HCells.
In soft-CDR mode, the DPA circuitry selects an optimal DPA clock phase to sample
the data and carry on the bit-slip operation and deserialization. The selected DPA
clock is also divided down by the deserialization factor and then forwarded to the
PLD core along with the de-serialized data. The LVDS block has an output called
divclkout for the forwarded clock signal. This signal is put on the newly introduced
PCLK (periphery clock) network. In HardCopy IV devices, every LVDS channel can
be used in soft-CDR mode and can drive the core via the PCLK network. Figure 8–10
shows the path enabled in soft-CDR mode.
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation