HC4GX15 Datasheet, PDF (321/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
1–57
Transmitter Local Clock Divider Block
f For more information about power states, refer to the PCI Express (PIPE) 2.0
specification available from Intel.
In the P1 power state, the transmitter output buffer is tri-stated because the
transmitter output buffer is in electrical idle. A high on the tx_detectrxloopback
port triggers the receiver detect circuitry to alter the transmitter output buffer
common mode voltage. The sudden change in common mode voltage effectively
appears as a step voltage at the tri-stated transmitter buffer output. If a receiver (that
complies with PIPE input impedance requirements) is present at the far end, the time
constant of the step voltage is higher. If a receiver is not present or is powered down,
the time constant of the step voltage is lower. The receiver detect circuitry snoops the
transmitter buffer output for the time constant of the step voltage to detect the
presence of the receiver at the far end. A high pulse is driven on the
pipephydonestatus port and 3'b011 is driven on the pipestatus port to indicate
that a receiver has been detected. There is some latency after asserting the
tx_detectrxloopback signal, before the receiver detection is indicated on the
pipephydonestatus port. For the signal timing to perform the receiver detect
operation, refer to Figure 1–108 on page 1–132.
1 The tx_forceelecidle port must be asserted at least 10 parallel clock cycles prior
to the tx_detectrxloopback port to ensure that the transmitter buffer is tri-stated.
PCI Express (PIPE) Electrical Idle
The HardCopy IV GX transmitter output buffer supports transmission of PIPE
Electrical Idle (or individual transmitter tri-state). This feature is only active in PIPE
mode. The tx_forceelecidle port puts the transmitter buffer in Electrical Idle
mode. This port has a specific functionality in each power state. For the signal timing
to perform the electrical idle transmission in PIPE mode, refer to Figure 1–107 on
page 1–131.
For use of the tx_forceelecidle signal under different power states, refer to the
PIPE specification 2.0.
Transmitter Local Clock Divider Block
Each transmitter channel contains a local clock divider block. It receives the
high-speed clock from the CMU0 PLL or CMU1 PLL and generates the high-speed serial
clock for the serializer and the low-speed parallel clock for the transmitter PCS
datapath. The low-speed parallel clock is also forwarded to the core fabric
(tx_clkout). The local clock divider block allows each transmitter channel to run at
/1, /2, or /4 of the CMU PLL data rate. The local clock divider block is used only in
non-bonded functional modes (for example, GIGE, SONET/SDH, and SDI mode).
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3