HC4GX15 Datasheet, PDF (369/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Receiver Channel Datapath
8B/10B Decoder in Single-Width Mode
Figure 1–87 shows the 8B/10B decoder in single-width mode.
Figure 1–87. 8B/10B Decoder in Single-Width Mode
datain [19:10]
8B/10B Decoder
(MSByte)
rx_dataout [15:8]
rx_ctrldetect[1]
rx_errdetect[1]
rx_disperr[1]
1–105
recovered clock or
tx_clkout[0]
datain[9:0]
Current Running Disparity
8B/10B Decoder
(LSByte)
rx_dataout[7:0]
rx_ctrldetect
rx_errdetect
rx_disperr
recovered clock or
tx_clkout[0]
In single-width mode, the 8B/10B decoder receives 10-bit data from the rate matcher
or word aligner (when rate matcher is disabled) and decodes it into an 8-bit
data + 1-bit control identifier. The decoded data is fed to the byte deserializer or the
receiver phase compensation FIFO (if byte deserializer is disabled).
1 The 8B/10B decoder is compliant to Clause 36 in the IEEE802.3 specification.
The 8B/10B decoder operates in single-width mode in the following functional
modes:
■ PCI Express (PIPE)
■ XAUI
■ GIGE
■ Serial RapidIO
■ Basic single-width
For PIPE, XAUI, GIGE, and Serial RapidIO functional modes, the ALTGX
MegaWizard Plug-In Manager forces selection of the 8B/10B decoder in the receiver
datapath. In Basic single-width mode, it allows you to enable or disable the 8B/10B
decoder depending on your proprietary protocol implementation.
Figure 1–88 shows a 10-bit code group decoded into an 8-bit data and a 1-bit control
identifier by the 8B/10B decoder in single-width mode.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3