HC4GX15 Datasheet, PDF (453/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Loopback Modes
1–189
Parallel Loopback Mode
You can configure a transceiver channel in this mode by setting the which protocol
will you be using? field to Basic and the which sub protocol will you be using? field
to BIST. You can only configure a Receiver and Transmitter transceiver channel in
this functional mode. You can configure a transceiver channel in this mode in either a
single-width or double-width configuration.
The BIST pattern generator and pattern verifier are located near the core fabric in the
PCS block of the transceiver channel. This placement allows for testing the complete
transmitter PCS and receiver PCS datapaths for bit errors. This mode is primarily
used for transceiver channel debugging, if needed.
The parallel loopback mode is available only with a built-in 16 bit incremental pattern
generator and verifier. The channel width is fixed to 16 bits in this mode. Also in this
mode, the incremental pattern 00-FF is looped back to the receiver channel at the PCS
functional block boundary before the PMA and is sent out to the tx_dataout port.
The received data is verified by the verifier. This loopback allows you to verify the
complete PCS block. The differential output voltage of the transmitted serial data on
the tx_dataout port is based on the selected V_OD settings. The datapath for parallel
loopback is shown in Figure 1–157. The incremental data pattern is not available to
the core logic for verification.
Figure 1–157. Enabled PCS Functional Blocks in Parallel Loopback
BIST incremental
pattern generator
Transmitter Channel PCS
Transmitter Channel PMA
Core
Fabric
TX
Phase
Compen-
sation
FIFO
BIST incremental
pattern verifier
RX
Compen-
sation
FIFO
Byte
Serializer
Byte
De-
serializer
8B/10B
Encoder
Receiver Channel PCS
Parallel
loopback
8B/10B
Decoder
Word
Aligner
Serializer
Receiver Channel PMA
De-
serializer
Receiver
CDR
Table 1–54 shows the enabled PCS functional blocks for single-width and
double-width mode. The last column in Table 1–54 shows the supported channel
width setting for parallel loopback.
Table 1–54. Enabled PCS Functional Blocks for Parallel Loopback
Configuration
Single-width mode
Double-width mode
8B/10B Encoder
Enabled
Enabled
Byte Serializer
Enabled
Disabled
Data Rate Range
600 Mbps to 3.125Gbps
1Gbps to 5Gbps
Supported Channel Width Setting
in the ALTGX MegaWizard Plug-In
Manager for Parallel Loopback
16
16
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3