HC4GX15 Datasheet, PDF (593/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Design Examples: Dynamic Reconfiguration Controller (ALTGX_RECONFIG)
2–135
Table 2–38. Step 1: Generate the ALTGX Instance for the GIGE Configuration (Part 3 of 3)
ALTGX MegaWizard Plug-In
Manager Option
Setting
What is the alternate transmitter
PLL logical reference index?
option
For the logical reference index option, select 1 or 0. The
Quartus II software uses the logical reference index to select
the PLL clock outputs for transmit and receive channels when
configured to SONET/SDH OC48 protocol. The MUX values
selected for the GIGE and SONET/SDH OC48 modes must be
different.
For example, if you select a logical reference index of 1 for the
SONET/SDH OC48 configuration, you need to select 0 for the
GIGE configuration. If you select the same values for the two
configurations, the transceiver behavior after reconfiguration
becomes unpredictable.
Reconfig 2 Screen
How should the receivers be
clocked? option
Select the Use the respective channel core clocks option.
Selecting this option creates the rx_clkout port. Select
this option because of the clocking differences between the
two modes (row 5 of Table 2–37 on page 2–131). The core
fabric logic can clock the receiver output of the ALTGX
instance with rx_clkout for SONET/SDH mode and
tx_clkout for GIGE mode.
How should the transmitters be
clocked? option
Select any option. Because this example assumes a one
channel reconfiguration in the transceiver block, the
preceding options will not make a difference. However, if the
number of channels used in channel reconfiguration is more
than one, Altera recommends you select the Share single
transmitter core clock between transmitters option to
conserve clock routing resources.
Check a control box to use the
corresponding control port:
option
Select signals in this option based on the requirements. The
signals in this tab can be selected only if the Channel
interface option is enabled in the Reconfig screen. For this
example, select the rx_byteorderalignstatus and
rx_a1a2sizeout signals because these signals are
required for SONET/SDH OC48 configuration.
Some of the signals are meaningful only for the modes for
which they are intended. For example, the
rx_byteorderalignstatus signal is only meaningful
in the SONET/SDH OC48 configuration. The core fabric logic
does not use these signals for GIGE configuration.
For more information about the protocol specific ALTGX
interface signals, refer to the Transceiver Port List in the
HardCopy IV GX Transceiver Architecture chapter in volume 3
of the HardCopy IV Device Handbook.
In the subsequent screens, select the required signals and complete the MegaWizard Plug-In
Manager instantiation.
© June 2009 Altera Corporation
HardCopy IV Device Handbook, Volume 3