HC4GX15 Datasheet, PDF (15/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV Device Family Overview
1–5
Features
Table 1–2. HardCopy IV E ASIC Features
HardCopyIV E
ASIC
HC4E25
HC4E35
Stratix IV E
Prototype
Device
EP4SE230
EP4SE360
EP4SE360
EP4SE530
EP4SE820
ASIC
Equivalent
Gates (1)
9.2 M
9.4 M
9.4 M
11.5 M
14.6 M
M9K
Blocks
864
864
1,248
1,280
1,320
M144K
Blocks
22
32
48
48
48
Total Dedicated
RAM Bits
(not including
MLABs) (2)
10,944 Kb
12,384 Kb
18,144 Kb
18,432 Kb
18,792 Kb
18 × 18-Bit
Multipliers
(FIR Mode)
1,288
1,040
1,040
1,024
960
PLLs
4
4
8
12 (3)
12 (3)
Notes to Table 1–2:
(1) This is the number of ASIC-equivalent gates available in the HardCopy IV E base array, shared between both adaptive logic module (ALM) logic
and DSP functions from a Stratix IV E FPGA prototype. The number of usable ASIC-equivalent gates is bounded by the number of ALMs in the
companion Stratix IV E FPGA device.
(2) MLAB RAMs are implemented with HCells in the HardCopy IV ASICs.
(3) This device has 12 PLLs in the F1517 package and eight PLLs in the F1152 package.
HardCopy IV ASIC and Stratix IV FPGA Mapping Paths
HardCopy IV devices offer pin-to-pin compatibility with the Stratix IV prototype,
making them drop-in replacements for the FPGAs. Therefore, the same system board
and software developed for prototyping and field trials can be retained, enabling the
lowest risk and fastest time-to-market for high-volume production.
HardCopy IV devices also offer non-socket replacement mapping paths to allow for
further cost reduction. For example, you can map the EP4SE230 device in the 780-pin
FBGA package to the HC4E25 device in the 484-pin FBGA package. Because the
pin-out for the two packages are not the same, you will need a separate board design
for the Stratix IV device and the HardCopy IV device.
1 For the non-socket replacement path, select I/Os in the Stratix IV device that can be
mapped to the HardCopy IV device. Not all I/Os in the Stratix IV device are available
in the HardCopy IV non-socket replacement device. Check the pin-out information
for both the Stratix IV device and HardCopy IV device to ensure that the I/Os can be
mapped, and select the companion device in the Quartus II project setting during
design development. By selecting the companion device, the Quartus II software
ensures that common resources and compatible I/Os are used during the mapping
from the Stratix FPGA to the HardCopy ASIC.
There are a number of FPGA prototype choices for each HardCopy IV device, as listed
in Table 1–3 and Table 1–4. To obtain the best value and the lowest system cost,
architect your system to maximize silicon resource utilization.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1