HC4GX15 Datasheet, PDF (389/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
1–125
Receiver Phase Comp FIFO in Register Mode
To remove the latency uncertainty through the receiver’s phase compensation FIFO,
select the Enable the RX phase comp FIFO in register mode option in the ALTGX
MegaWizard Plug-In Manager. In register mode, the phase compensation FIFO acts as
a register and thereby removes the uncertainty in latency. The latency through the
phase compensation FIFO in register mode is one clock cycle.
This mode is available in:
■ Basic single-width mode with 8-bit channel width and 8B/10B encoder enabled or
10-bit channel width with 8B/10B disabled.
■ Basic double-width mode with 16-bit channel width and 8B/10B encoder enabled
or 20-bit channel width with 8B/10B disabled.
Transmitter Bit Slipping
The transmitter is bit slipped to achieve deterministic latency. To use this feature,
select the Create the ‘tx_bitslipboundaryselect[4:0] port to control the number of
bits slipped in the TX bitslipper option in the ALTGX MegaWizard Plug-In Manager.
The tx_bitslipboundaryselect[4:0] input port is used to set the number of
bits that the transmitter block needs to slip.
■ In the Basic single—width mode with 8/10-bit channel width you can slip zero
to 9 bits.
■ In the Basic double—width mode with 16/20-bit channel width you can slip zero
to 19 bits.
PCI Express (PIPE) Mode
Intel Corporation has developed a PHY interface for the PIPE Architecture
specification to enable implementation of a PIPE-compliant physical layer device. The
PIPE specification also defines a standard interface between the physical layer device
and the media access control layer (MAC). Version 2.0 of the PIPE specification
provides implementation details for a PIPE-compliant physical layer device at both
Gen1 (2.5 GT/s) and Gen2 (5 GT/s) signaling rates.
To implement a Version 2.0 PIPE-compliant PHY, you must configure the
HardCopy IV GX transceivers in PIPE functional mode. HardCopy IV GX devices
have built-in PIPE hard IP blocks that you can use to implement the PHY-MAC layer,
data link layer, and transaction layer of the PIPE protocol stack. You can also bypass
the PIPE hard IP blocks and implement the PHY-MAC layer, data link layer, and
transaction layer in the FGPA fabric using a soft IP. If you enable the PIPE hard IP
blocks, the HardCopy IV GX transceivers interface with these hard IP blocks.
Otherwise, the HardCopy IV GX transceivers interface with the core fabric.
You can configure the HardCopy IV GX transceivers in PIPE functional mode using
one of the following two methods:
■ ALTGX MegaWizard Plug-In Manager if you do not use the PIPE hard IP block
■ PIPE Compiler if you use the PIPE hard IP block
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3