HC4GX15 Datasheet, PDF (289/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
1–25
CMU Channels
You can select the input reference clock to the CMU0 PLL from multiple clock sources.
The various clock sources are:
■ PLL cascade clock—the PLL cascade clock is the output from the general purpose
PLLs in the core fabric
■ Global clock line—the input reference clock from the dedicated CLK pins are
connected to the global clock line
■ refclk0—dedicated REFCLK in the transceiver block
■ refclk1—dedicated REFCLK in the transceiver block
■ Inter transceiver block (ITB) lines—the ITB lines connect refclk0 and refclk1
of all other transceiver blocks on the same side of the device
The CMU0 PLL generates the high-speed clock from the input reference clock. The
phase frequency detector (PFD) tracks the voltage-controlled oscillator (VCO) output
with the input reference clock.
The VCO in the CMU0 PLL is half rate and runs at half the serial data rate. The CMU0
PLL uses two multiplier blocks (/M and /L) in the feedback path (shown in
Figure 1–9) to generate the high-speed clock needed to support a native data rate
range of 600 Mbps to 6.5 Gbps.
1 The ALTGX MegaWizard Plug-In Manager provides the list of input reference clock
frequencies based on the data rate selected. The Quartus II software automatically
selects the /M and /L settings based on the input reference clock frequency and serial
data rate.
Each CMU PLL (CMU0 PLL and CMU1 PLL) has a dedicated pll_locked signal that is
asserted to indicate that the CMU PLL is locked to the input reference clock.
PLL Bandwidth Setting
You can program the PLL bandwidth setting using the ALTGX MegaWizard Plug-In
Manager. The bandwidth of a PLL is the measure of its ability to track input clock and
jitter. It is determined by the –3 dB frequency of the closed-loop gain of the PLL. There
are three bandwidth settings: high, medium, and low.
■ The high bandwidth setting filters out internal noise from the VCO because it
tracks the input clock above the frequency of the internal VCO noise.
■ With the low bandwidth setting, if the noise on the input reference clock is greater
than the internal noise of the VCO, the PLL filters out the noise above the –3 dB
frequency of the closed-loop gain of the PLL.
■ The medium bandwidth setting is a compromise between the high and low
settings.
The –3 dB frequencies for these settings can vary because of the non-linear nature and
frequency dependencies of the circuit.
Power Down CMU0 PLL
You can power down the CMU0 PLL by asserting the pll_powerdown signal.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3