HC4GX15 Datasheet, PDF (221/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 3: Mapping Stratix IV Device Resources to HardCopy IV Devices
3–19
Designing with HardCopy IV I/Os
HardCopy IV ASICs support LVDS on all I/O banks. True LVDS makes use of
dedicated LVDS I/O buffers that are optimized for performance. There are true LVDS
input and output buffers at the left and right side I/O banks. There are true LVDS
input buffers on the top and bottom I/O banks only.
You can configure all I/Os in all banks as emulated LVDS output buffers. Emulated
output buffers make use of single-ended buffers and an external resistor network to
mimic LVDS operation. Emulated LVDS is useful for low-speed, low-voltage
differential applications.
f For more information about high-speed I/O performance, refer to the High Speed
Differential I/O Interface with DPA in HardCopy IV Devices chapter.
All dedicated circuitry for high-speed differential I/O applications are located in the
left and right I/O banks of the Stratix IV and HardCopy IV devices. The top and
bottom I/O banks also have support for high-speed receiver applications that do not
require the use of the DPA, synchronizer, data realignment, and differential
termination. Top and bottom differential I/O buffers have a slower data rate than the
high-speed receivers on the left and right I/O banks.
Table 3–13 shows the LVDS channels supported in HardCopy IV GX and
Stratix IV GX companion devices.
Table 3–13. LVDS Channels Supported In HardCopy IV GX and Stratix IV GX Companion Devices (Note 1), (2) (Part 1 of 3)
780-Pin FineLine BGA
1152-Pin FineLine BGA 1152-Pin FineLine BGA
1152-Pin FineLine BGA
1517-Pin FineLine BGA
HardCopy I V
GX ASIC
Stratix IV
GX FPGA
Prototype
HardCopy
IV GX ASIC
Stratix IV
Stratix IV
GX FPGA HardCopy IV GX FPGA
Prototype GX ASIC Prototype
Stratix IV
HardCopy IV GX FPGA HardCopy IV
GX ASIC Prototype GX ASIC
Stratix IV
GX FPGA
Prototype
Bank
1A
1B
1C
2A
2B
2C
3A
(5)
3B
(5)
HC4GX15
8Rx + 8Tx
—
6Rx + 6Tx
8Rx + 8Tx
—
6Rx + 6Tx
10Rx +
10eTx
or
20eTx
—
EP4SGX70
EP4SGX110
EP4SGX180
EP4SGX230
8Rx + 8Tx
—
6Rx + 6Tx
8Rx + 8Tx
—
6Rx + 6Tx
10Rx +
10eTx
or
20eTx
—
HC4GX25
8Rx + 8Tx
—
6Rx + 6Tx
8Rx + 8Tx
—
6Rx + 6Tx
10Rx +
10eTx
or
20eTx
—
EP4SGX110
HC4GX25
EP4SGX180
EP4SGX230
EP4SGX290
EP4SGX360
EP4SGX530
(3)
HC4GX35
EP4SGX230
EP4SGX360
EP4SGX530
(3)
HC4GX35
EP4SGX180
EP4SGX230
EP4SGX290
EP4SGX360
EP4SGX530
(4)
8Rx + 8Tx
12Rx +
12Tx
12Rx +
12Tx
12Rx +
12Tx
12Rx +
12Tx
12Rx +
12Tx
12Rx +
12Tx
—
—
—
—
—
—
—
6Rx + 6Tx
10Rx +
10Tx
10Rx +
10Tx
10Rx +
10Tx
10Rx +
10Tx
10Rx +
10Tx
10Rx +
10Tx
8Rx + 8Tx
-
12Rx +
-
12Rx +
12Rx +
12Rx +
12Tx
12Tx
12Tx
12Tx
—
—
—
—
—
—
—
6Rx + 6Tx
-
10Rx +
-
10Rx +
10Rx +
10Rx +
10Tx
10Tx
10Tx
10Tx
10Rx +
10eTx
or
20eTx
10Rx +
10eTx
or
20eTx
10Rx +
10eTx
or
20eTx
10Rx +
10eTx
or
20eTx
10Rx +
10eTx
or
20eTx
10Rx +
10eTx
or
20eTx
10Rx +
10eTx
or
20eTx
—
6Rx + 6eTx 6Rx + 6eTx 6Rx + 6eTx 6Rx + 6eTx 6Rx + 6eTx 6Rx + 6eTx
or
or
or
or
or
or
12eTx
12eTx
12eTx
12eTx
12eTx
12eTx
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 2