HC4GX15 Datasheet, PDF (292/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–28
Chapter 1: HardCopy IV GX Transceiver Architecture
CMU Channels
CMU1 Channel
The CMU1 channel shown in Figure 1–12 contains the CMU1 PLL that provides the
high-speed clock to the transmitter channels within the transceiver block. The
CMU1 PLL is similar to the CMU0 PLL. The functionality of the CMU0 PLL is described
in “CMU0 PLL” on page 1–24.
Figure 1–12. CMU1 Channel (Grayed Area Shows the Inactive Block)
pll_locked
pll_powerdown
PLL Cascade Clock
Global Clock Line
Dedicated refclk0
Dedicated refclk1
ITB Clock Lines
6
CMU1 PLL
Input
Reference
Clock
CMU1 PLL
CMU1 PLL
High-Speed
Clock
CMU1 Clock
Divider
CMU1 Channel
The CMU1 PLL generates the high-speed clock that is only used in non-bonded
functional modes. In non-bonded functional modes, the transmitter channels within
the transceiver block can receive a high-speed clock from either of the two CMU PLLs
and uses local dividers to provide clocks to its PCS and PMA blocks.
Power Down CMU1 PLL
You can power down the CMU1 PLL by asserting the pll_powerdown signal.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation