HC4GX15 Datasheet, PDF (531/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 2: HardCopy IV GX Dynamic Reconfiguration
2–73
Description of Transceiver Channel Reconfiguration Modes
Figure 2–36 shows the correct input reference clock connections when reusing a .mif.
Figure 2–36. Correct Input Reference Clock Connections When Reusing a .mif
HardCopy IV GX Device
156.25 MHz
pll_inclk_rx_cruclk[0]
pll_inclk_rx_cruclk[1]
Transceiver Block 0
ALTGX
Instance 1
125 MHz
pll_inclk_rx_cruclk[0]
pll_inclk_rx_cruclk[1]
Transceiver Block 1
ALTGX
Instance 2
1 You can reuse the .mif generated for a transceiver channel on one side of the device,
for a transceiver channel on the other side of device, only if the input reference clock
frequencies and order of the pll_inclk_rx_cruclk [] ports in the ALTGX
instances on both sides are identical.
In addition to the input reference clock requirements when reusing a .mif, refer to
“The logical_tx_pll_sel and logical_tx_pll_sel_en Ports” on page 2–109 for additional
ways to reuse a .mif.
The logical_channel_address Port in .mif-Based Dynamic Reconfiguration Modes
Based on the value you set at the logical_channel_address [8:0] port, the
dynamic reconfiguration controller writes the .mif contents into the transceiver
channel you specify. This signal is enabled only when the number of channels
controlled by the dynamic reconfiguration controller is more than one. Because
transceiver channel reconfiguration is done on a per-channel basis, you must use this
signal and provide the necessary logical channel address to write the .mif words
successfully into the channel. For more information about the
logical_channel_address port, refer to “Dynamic Reconfiguration Controller
Port List” on page 2–11.
1 In CMU PLL reconfiguration mode, use logical_channel_address to specify the
transceiver channel that the CMU PLL (under reconfiguration) is connected to.
© June 2009 Altera Corporation
HardCopy IV Device Handbook, Volume 3