HC4GX15 Datasheet, PDF (513/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 2: HardCopy IV GX Dynamic Reconfiguration
2–55
PMA Controls Reconfiguration
Figure 2–21. Method 1—Write Transaction Waveform
reconfig_clk
write_all
rx_tx_duplex_sel [1:0] (1)
2’b00
2’b10
logical_address_channel [1:0] (2)
2’b00
2’b01
busy
tx_vodctrl [2:0]
3’b000
3’b111
Notes to Figure 2–21:
(1) Consider that you want to write to only the transmitter portion of the channel.
(2) This waveform assumes that the number of channels connected to the dynamic reconfiguration controller is four. Therefore, the
logical_channel_address port is 2 bits wide.
Read Transaction
In this example, you want to read the existing V_OD values from the transmit V_OD
control registers of the transmitter portion of a specific channel controlled by the
ALTGX_RECONFIG instance. The read transaction in this scenario is explained in the
following steps:
1. Set the input logical_channel_address port to the logical channel address of
the transceiver channel whose PMA controls you want to read (for example,
tx_vodctrl_out).
2. Set the rx_tx_duplex_sel[1:0] port to 2'b10 so that only the transmit PMA
controls are read from the transceiver channel.
3. Ensure that the busy signal is low before you start a read transaction.
4. Assert the read signal for one reconfig_clk clock cycle. This initiates the read
transaction.
The busy output status signal is asserted high to indicate that the dynamic
reconfiguration controller is busy reading the PMA control values. Once the read
transaction has completed, the busy signal goes low. The data_valid signal gets
asserted indicating that the data available at the read control signal is valid.
© June 2009 Altera Corporation
HardCopy IV Device Handbook, Volume 3