HC4GX15 Datasheet, PDF (543/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Description of Transceiver Channel Reconfiguration Modes
Figure 2–42. Receiver Core Clocking for Option 1
ASIC Core
Transceiver Block
tx_clkout[0]
TX0 (2 Gbps)
RX0
TX1 (2 Gbps)
RX1
TX2 (2 Gbps)
RX2
TX3 (2 Gbps)
RX3
2–85
CMU1 PLL
CMU0 PLL
Four regular transceiver channels
configured at Basic 2G with
Rate Matching and set up to
switch to 3.125 Gbps with Rate Matching
Low speed parallel clock generated by the TX0 local divider (tx_clkout[0])
High speed serial clock generated by the CMU0 PLL
High speed serial clock generated by the CMU1 PLL
© June 2009 Altera Corporation
HardCopy IV Device Handbook, Volume 3