HC4GX15 Datasheet, PDF (379/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Receiver Channel Datapath
1–115
Figure 1–98 shows user-controlled byte ordering in Basic double-width Mode.
Figure 1–98. User-Controlled Byte Ordering in Basic Double-Width Mode
Transmitter Channel
Receiver
tx_datain[31:16] _D2D3
(MSByte)
tx_datain[15:0]
(LSByte)
D0D1
D4D5
B1B2
D8D9
D6D7
xxxx
B1B2
Byte
Serializer
Byte
Deserializer
D0D1 B1B2
D6D7 B1B2
xxxx
D2D3 D4D5 D8D9
Byte
Ordering
D0D1
xxxx
P1P2
D2D3
D4D5 D8D9
B1B2 D6D7
xxxx ^{rx_dataout [31:16]}
(MSByte)
B1B2 ^{rx_dataout[15:0]}
(LSByte)
rx_enabyteord
rx_byteorderalignstatus
Receiver Phase Compensation FIFO
The receiver phase compensation FIFO in each channel ensures reliable transfer of
data and status signals between the receiver channel and the core fabric. The receiver
phase compensation FIFO compensates for the phase difference between the parallel
receiver PCS clock (FIFO write clock) and the core fabric clock (FIFO read clock).
The receiver phase compensation FIFO operates in one of the following two modes:
■ Low latency mode—The Quartus II software automatically configures the receiver
phase compensation FIFO in low latency mode in all functional modes. In this
mode, the FIFO is four words deep and the latency through the FIFO is two to
three parallel clock cycles (pending characterization).
■ High latency mode—In this mode, the FIFO is eight words deep and the latency
through the FIFO is four to five parallel clock cycles (pending characterization).
The receiver phase compensation FIFO write clock source varies with the receiver
channel configuration. Table 1–28 shows the receiver phase compensation FIFO write
clock source in different configurations.
Table 1–28. Receiver Phase Compensation FIFO Write Clock Source (Part 1 of 2)
Receiver Phase Compensation FIFO Write Clock
Configuration
Non-bonded channel
configuration with rate matcher
Non-bonded channel
configuration without rate
matcher
Without Byte Serializer
Parallel transmitter PCS clock from the
local clock divider in the associated
channel (tx_clkout)
Parallel recovered clock from the receiver
PMA in the associated channel
(rx_clkout)
With Byte Serializer
Divide-by-two version of the parallel
transmitter PCS clock from the local clock
divider in the associated channel
(tx_clkout)
Divide-by-two version of the parallel
recovered clock from the receiver PMA in
the associated channel (rx_clkout)
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3