HC4GX15 Datasheet, PDF (121/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 8: High-Speed Differential I/O Interfaces and DPA in HardCopy IV Devices
Synchronizer
Figure 8–10. Soft-CDR Mode Data and Clock Path (Note 1)
Data to Core
10
Deserializer
ReTimed
Data
Bit Slip
DPA
LVDS Data
8–11
CLK_BS_DES
DPA
CLOCK
TREE
PLL
Ref
Clock
DPA CLK
PCLK
Divide Down
and
Clock Forwarding
core
Note to Figure 8–10:
(1) The synchronizer FIFO is bypassed in soft-CDR mode. The reference clock frequency must be suitable for the PLL to generate a clock that matches
the data rate of the interface. The DPA circuitry can track parts per million (PPM) differences between the reference clock and the data stream.
Synchronizer
The synchronizer is a 1-bit × 6-bit deep FIFO buffer that compensates for the phase
difference between the recovered clock from the DPA circuit and the diffioclk that
clocks the rest of the logic in the receiver. The synchronizer can only compensate for
phase differences, not frequency differences between the data and the receiver ’s
inclk.
An optional port (rx_fifo_reset) is available to the internal logic to reset the
synchronizer. The synchronizer is automatically reset when the DPA first locks to the
incoming data. Altera recommends using rx_fifo_reset to reset the synchronizer
when the DPA signals a loss-of-lock condition beyond the initial locking condition.
Pre-Emphasis and Output Differential Voltage (VOD)
HardCopy IV LVDS transmitters support four pre-emphasis and four VOD settings.
Pre-emphasis increases the amplitude of the high frequency component of the output
signal, and helps compensate for the frequency dependent attenuation along the
transmission line. Figure 8–11 shows an LVDS output with pre-emphasis. The
overshoot is produced by pre-emphasis. This overshoot must not be included in the
VOD voltage. The definition of VOD is also shown in Figure 8–11.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1