HC4GX15 Datasheet, PDF (41/668 Pages) Altera Corporation – HardCopy IV Device Handbook

5. Clock Networks and PLLs in
HardCopy IV Devices
HIV51005-2.1
This chapter provides a general description of clock networks and phase-locked loops
(PLLs) in HardCopy^® IV devices.
HardCopy IV devices support a hierarchical clock structure and multiple PLLs with
advanced features equivalent to Stratix^® IV devices. The large number of clocking
resources in combination with clock synthesis precision offered by the PLLs, provides
a complete clock management solution for your designs. HardCopy IV devices
provide dedicated global clock networks (GCLKs), regional clock networks (RCLKs),
and periphery clock networks (PCLKs). These clocks are organized into a hierarchical
clock structure that provides up to 192 unique clock domains for the entire device and
up to 60 unique clock sources per device quadrant. Altera’s Quartus^® II software
compiler automatically turns off clock networks not used in the design, thereby
reducing overall power consumption of the device.
HardCopy IV devices deliver abundant PLL resources with up to 12 PLLs per device
and up to 10 outputs per PLL. These PLLs are feature rich, supporting advanced
capabilities such as clock switchover, dynamic phase shifting, PLL reconfiguration,
and reconfigurable bandwidth. HardCopy IV PLLs also support external feedback
mode, spread-spectrum tracking, and post-scale counter cascading features. The
Quartus II software enables the PLLs and their features without requiring any
external devices.
1 All Stratix IV PLL features are supported by HardCopy IV PLLs.
f For more information about clock networks and PLLs, refer to the Clock Networks and
PLLs in Stratix IV Devices chapter in volume 1 of the Stratix IV Device Handbook.
This chapter contains the following sections:
■ “Clock Networks in HardCopy IV Devices”
■ “PLLs in HardCopy IV Devices” on page 5–3
■ “Design Considerations” on page 5–7
Clock Networks in HardCopy IV Devices
HardCopy IV devices offer the same clock network resources and features as
Stratix IV devices. Clock resources that are used in Stratix IV devices are mapped to
equivalent clock resources in HardCopy IV devices, preserving the clocking functions.
Unused clock resources are powered down to reduce power consumption.
Clock Network Resources
Similar to Stratix IV devices, HardCopy IV devices have up to 32 dedicated single-
ended clock pins or 16 dedicated differential clock pins (CLK[0:15]p and
CLK[0:15]n) that can drive either the GCLK or RCLK networks. These clock pins are
arranged in the middle of the four sides of the HardCopy IV device.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1