HC4GX15 Datasheet, PDF (87/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 7: External Memory Interfaces in HardCopy IV Devices
7–21
Memory Interfaces Pin Support
Table 7–7. DQ/DQS Group in HardCopy IV Modular I/O Banks
Modular I/O Bank Size (1)
Maximum Possible
Number of ×4 Groups
Maximum Possible
Number of ×8/×9
Groups
Maximum Possible
Number of ×16/×18
Groups
Maximum Possible
Number of ×32/×36
Groups
24 pins
4 (2)
2
1
0
32 pins
5 (3)
2
1
0
40 pins
6
3
1
0
48 pins
8
4
2
1
Notes to Table 7–7:
(1) This I/O pin count does not include dedicated clock inputs or the dedicated corner PLL clock inputs.
(2) Some of the ×4 groups may use the R_UP and R_DN pins. You cannot use these groups if you use the HardCopy IV calibrated OCT feature.
(3) The actual maximum number of ×4 groups for an I/O bank with 32 pins is four in the HardCopy IV devices.
Optional Parity, DM, BWSn, ECC, and QVLD Pins
You can use any DQ pin from the same DQS/DQ group for data as parity pins in
HardCopy IV devices. The HardCopy IV device family supports parity in the ×8/×9,
×16/×18, and ×32/×36 modes. There is one parity bit available per eight bits of data
pins. Use any of the DQ (or D) pins in the same DQS/DQ group as data for parity
because parity bits are treated, set, and generated similar to a DQ pin.
The DM pins are only required when writing to DDR3, DDR2, DDR SDRAM, and
RLDRAM II devices. QDRII+ and QDRII SRAM devices use the BWSn signal to select
which byte to write into the memory. A low on the DM or BWSn signals indicates the
write is valid. If the DM or BWSn signal is high, the memory masks the DQ signals. If
the system does not require write data masking, connect the memory DM pins low to
indicate every write data is valid. You can use any of the DQ pins in the same
DQS/DQ group as write data for the DM or BWSn signals.
Each group of DQS and DQ signals in DDR3, DDR2, and DDR SDRAM devices
requires a DM pin. There is one DM pin per RLDRAM II device and one BWSn pin
per nine bits of data in ×9, ×18, and ×36 QDRII+/QDRII SRAM. The ×8 QDRII SRAM
device has two BWSn pins per eight data bits, which are referred to as the NWSn pins.
Generate the DM or BWSn signals using DQ pins and configure the signals similarly to
the DQ (or D) output signals. HardCopy IV devices do not support the DM signal in ×4
DDR3 SDRAM or in ×4 DDR2 SDRAM interfaces with differential DQS signaling.
Some DDR3, DDR2, and DDR SDRAM devices or modules support error correction
coding (ECC), which is a method of detecting and automatically correcting errors in
data transmission. In 72-bit DDR3, DDR2, or DDR SDRAM interfaces, the typical
eight ECC pins are used in addition to the 64 data pins. Connect the DDR3, DDR2,
and DDR SDRAM ECC pins to a HardCopy IV device DQS/DQ group. These signals
are also generated similar to DQ pins. The memory controller requires encoding and
decoding logic for the ECC data. You can also use the extra byte of data for other error
checking methods.
QVLD pins are used in RLDRAM II and QDRII+ SRAM interfaces to indicate the read
data availability. There is one QVLD pin per memory device. A high on the QVLD pin
indicates that the memory is outputting the data requested. Similar to DQ inputs, this
signal is edge-aligned with the read clock signals (CQ/CQn in QDRII+/QDRII SRAM
and QK/QK# in RLDRAM II) and is sent half a clock cycle before data starts from the
memory. The QVLD pin is not used in the ALTMEMPHY solution for QDRII+ SRAM.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1