HC4GX15 Datasheet, PDF (418/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–154
Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
XAUI Mode Datapath
Figure 1–123 shows the ALTGX megafunction transceiver datapath when configured
in XAUI mode.
Figure 1–123. Transceiver Datapath in XAUI Mode
tx_coreclk[3:2]
rx_coreclk[3:2]
coreclkout
Core Fabric-Transceiver
Interface Clock
Core
Fabric
tx_coreclk[1:0]
Channel 3
Channel 2
TX Phase
Compensation
FIFO
wrclk
rdclk
Byte
Serializer
wrclk
rdclk
Transmitter Channel PCS
8B/10B
Encoder
Transmitter Channel PMA
Serializer
Channel 3
Channel 2
RX Phase
Compensation
FIFO
/2
Low-Speed Parallel Clock from CMU 0 Click Divider
Byte
De-
serializer
Receiver Channel PCS Receiver Channel PMA
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
De-
serializer
CDR
/2
Input
Reference
Clock
CMU1_PLL
Input
Reference
Clock
CMU0_PLL
Channel 1
Channel 0
TX Phase
Compensation
FIFO
wrclk
rdclk
Ch0 Parallel
Ch2 Parallel
Recovered Clock
Recovered Clock
/2
Low-Speed Parallel Clock from CMU 0 Clock Divider
CMU1
Clock
Divider
CMU1_Channel
CMU0_Channel
CMU0
Clock
Divider
Low-Speed Parallel Clock
High-Speed Serial Clock
Byte
Serializer
wrclk
rdclk
Transmitter Channel PCS
Transmitter Channel PMA
8B/10B
Encoder
Serializer
Channel 1
Channel 0
RX Phase
Compensation
FIFO
/2
Low-Speed Parallel Clock from CMU 0 Clock Divider
Byte
De-
serializer
Receiver Channel PCS Receiver Channel PMA
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
De-
Serializer
CDR
rx_coreclk[1:0]
Ch0 Parallel
Recovered Clock
Ch0 Parallel
Recovered Clock
/2
Low-Speed Parallel Clock from CMU 0 Clock Divider
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation