HC4GX15 Datasheet, PDF (301/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
1–37
Transmitter Channel Datapath
Figure 1–21. Transmitter Channel Datapath
PCI
Express
hardIP
PIPE
Interface
TX Phase
Compensation
FIFO
Transmitter Channel PCS
Byte
Serializer
8B/10B
Encoder
Transmitter Channel PMA
Serializer
Core
Fabric
TX Phase Compensation FIFO
The TX phase compensation FIFO interfaces the transmitter channel PCS and the core
fabric PCI Express (PIPE) interface. It compensates for the phase difference between
the low-speed parallel clock and the core fabric interface clock. The TX phase
compensation FIFO operates in low-latency and high-latency mode. Figure 1–22
shows the datapath and clocking of the TX phase compensation FIFO.
Figure 1–22. TX Phase Compensation FIFO
Data Path from the Core
Fabric or PIPE Interface
TX Phase
Compensation
FIFO
Data Path to the Byte Serializer
or the 8B/10B Encoder or
Serializer
wr_clk
rd_clk
tx_coreclk
tx_clkout
coreclkout
TX phase compensation FIFO:
■ In low-latency mode, the FIFO is four words deep. The latency through the FIFO is
two to three core fabric parallel clock cycles (pending characterization).
Low-latency mode is the default setting for every mode.
■ In high-latency mode, the FIFO is eight words deep. The latency through the FIFO
is approximately four to five parallel cycles (pending characterization).
In non-bonded functional modes such as GIGE, the read port of the phase
compensation FIFO is clocked by the low-speed parallel clock. The write clock is fed
by the tx_clkout port of the associated channel.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3