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HC4GX15 Datasheet, PDF (141/668 Pages) Altera Corporation – HardCopy IV Device Handbook
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Chapter 9: Hot Socketing and Power-On Reset in HardCopy IV Devices
9–3
Power-On Reset Circuitry
The POR circuit monitors the voltage level of power supplies (VCC, VCCPD, and VCCAUX)
and keeps the I/O pins tri-stated until the device is in user mode. The weak pull-up
resistor (R) in the HardCopy IV input/output element (IOE) keeps the I/O pins from
floating. The voltage tolerance control circuit permits the I/O pins to be driven by
external voltages before VCC, VCCIO, VCCPGM, and/or VCCPD supplies are powered, and it
prevents the I/O pins from driving out when the device is not in user mode.
Power-On Reset Circuitry
A power-on reset event occurs if all the POR-monitored power supplies, shown in
Table 9–1 reach the recommended operating range within a certain period of time
(specified as power supply ramp time, TRAMP). Figure 9–2 shows the power supply
specification. All power supplies’ voltages have to rise monotonically within TRAMP.
This ensures the voltage levels do not remain indeterminate for a long time during
power-up.
Figure 9–2. Power Supply Ramp Behavior
Voltage
: Ideal
: Acceptable (see TRAMP specs)
T RAMP
(min)
T RAMP
(max)
All power supplies should reach full rail
Time
HardCopy IV devices provide a dedicated input pin (PORSEL) to select a TRAMP range
from 4 ms to 12 ms, or from 100 ms to 300 ms for all power supplies to ramp up. When
the PORSEL pin is connected to ground, the TRAMP can be from 100 ms to 300 ms. When
the PORSEL pin is set to high, the TRAMP can be from 4 ms to 12 ms.
The POR block consists of a regulator POR, satellite POR, and main POR to check the
power supply levels for proper device operation. The regulator POR monitors the
internal reference voltage for the temperature sensing diode and POR. The satellite
POR monitors VCC, VCCPD, VCCPGM, and VCCAUX power supplies to ensure proper device
operation. It also checks for functionality of I/O level shifters powered by VCCPD and
VCCPGM during power-up mode. The main POR collects signals from both regulator
and satellite PORs and generates POR pulse according to the PORSEL signal. A
simplified block diagram of the POR block is shown in Figure 9–3.
All configuration-related dedicated and dual function I/O pins must be powered by
VCCPGM.
© December 2008 Altera Corporation
HardCopy IV Device Handbook, Volume 1
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