HC4GX15 Datasheet, PDF (397/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
1–133
■ For 8-bit transceiver channel width configurations, you must drive
tx_forcedispcompliance high in the same parallel clock cycle as the first
/K28.5/ of the compliance pattern on the tx_datain port.
■ For 16-bit transceiver channel width configurations, you must drive only the LSB
of tx_forcedispcompliance[1:0] high in the same parallel clock cycle as
/K28.5/D21.5/ of the compliance pattern on the tx_datain port.
Figure 1–110 and Figure 1–111 show the required level on the
tx_forcedispcompliance signal while transmitting the compliance pattern in
8-bit and 16-bit channel width configurations, respectively.
Figure 1–110. Compliance Pattern Transmission Support, 8-Bit Channel Width Configurations
K28.5
D21.5
K28.5
D10.2
K28.5
D21.5
K28.5
D10.2
tx_datain[7:0]
BC
B5
BC
4A
BC
B5
BC
4A
tx_ctrldetect
tx_forcedispcompliance
Figure 1–111. Compliance Pattern Transmission Support, 16-Bit Channel Width Configurations
tx_datain[15:0]
/K28.5/D21.5/
B5BC
/K28.5/D10.2/
BC4A
/K28.5/D21.5/
B5BC
/K28.5/D10.2/
BC4A
tx_ctrldetect[1:0]
01
tx_forcedispcompliance[1:0]
01
00
Power State Management
The PCI Express (PIPE) specification defines four power states—P0, P0s, P1, and
P2— that the physical layer device must support to minimize power consumption.
■ P0 is the normal operating state during which packet data is transferred on the
PIPE link.
■ P0s, P1, and P2 are low-power states into which the physical layer must transition
as directed by the PHY-MAC layer to minimize power consumption.
The PIPE specification provides the mapping of these power states to the LTSSM
states specified in the PIPE Base Specification 2.0. The PHY-MAC layer is responsible
for implementing the mapping logic between the LTSSM states and the four power
states in the PIPE-compliant PHY.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3