HC4GX15 Datasheet, PDF (47/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 5: Clock Networks and PLLs in HardCopy IV Devices
5–7
Design Considerations
Design Considerations
To ensure that your Stratix IV design can be successfully mapped to the HardCopy IV
design, follow these general guidelines when implementing your design. The
following guidelines help make your design robust, ensuring it meets timing closure
and achieves the performance you need:
■ Match the PLL resources used in HardCopy IV devices and Stratix IV devices in
order to successfully map your design from the FPGA design to the ASIC design,
or vice-versa. This is necessary to ensure that all the resources used and the
functions implemented in both designs match. Make sure to select the companion
device during device selection in the Quartus II software. Doing this restricts the
Quartus II software to resources that are common to both the FPGA and ASIC
devices and ensures that the design can map successfully. Refer to Table 5–2 for
the available PLLs in the HardCopy IV series devices for non-socket migration.
■ Enable PLL reconfiguration for your design if it uses PLLs. The PLL settings in
HardCopy IV devices may require different settings from the Stratix IV PLLs
because of the different clock tree lengths and PLL compensations. By enabling
PLL reconfiguration, you can adjust your PLL settings on the HardCopy IV device
after the silicon has been fabricated. This allows you to fine tune and further
optimize your system performance.
■ Use dedicated clock input pins to drive the PLL reference clock inputs,
particularly if your design is interfacing with an external memory. This minimizes
reference clock input jitter to the PLLs, providing more margin for your design.
When you cascade PLLs for the ALTMEMPHY, ensure that:
■ The input clock to the ALTMEMPHY PLL is fed by a dedicated input
■ If the ALTMEMPHY PLL is fed by another PLL, the source PLL
■ input must be fed by a dedicated input pin
■ must be in no compensation mode
■ If the input clock to the ALTMEMPHY is fed by another PLL, the ALTMEMPHY
PLL's input clock must be from a dedicated clock output from the source PLL.
Document Revision History
Table 5–5 lists the revision history for this chapter.
Table 5–5. Document Revision History
Date
January 2010
June 2009
December 2008
Version
2.1
2.0
1.0
Changes Made
■ Updated Table 5–2.
■ Minor text edits.
Added non-socket information and new part numbers.
Initial release.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1