HC4GX15 Datasheet, PDF (337/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
1–73
Receiver Channel Datapath
Figure 1–57 shows the deserializer operation in single-width mode with a 10-bit
deserialization factor.
Figure 1–57. Deserializer Operation in Single-Width Mode
Received Data
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Clock
Recovery
Unit
High-Speed Serial Recovered Clock
Low-Speed Parallel Recovered Clock
10 _{To Word}
Aligner
Figure 1–58 shows the serial bit order of the deserializer block input and the parallel
data output of the deserializer block in single-width mode with a 10-bit
deserialization factor. The serial stream (0101111100) is deserialized to a value 10'h17C.
The serial data is assumed to be received LSB to MSB.
Figure 1–58. Deserializer Bit Order in Single-Width Mode
Low-Speed Parallel Clock
High-Speed Serial Clock
datain
00 1 1 1 1 1 0 1 0 1 1 0 0 0 0 0 1 0 1
dataout
0101111100
1010000011
Word Aligner
Because the data is serialized before transmission and then deserialized at the
receiver, it loses the word boundary of the upstream transmitter upon deserialization.
The word aligner receives parallel data from the deserializer and restores the word
boundary based on a pre-defined alignment pattern that must be received during link
synchronization.
Serial protocols such as PCI Express (PIPE), XAUI, Gigabit Ethernet, Serial RapidIO,
and SONET/SDH, specify a standard word alignment pattern. For proprietary
protocols, the HardCopy IV GX transceiver architecture allows you to select a custom
word alignment pattern specific to your implementation.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3