HC4GX15 Datasheet, PDF (657/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: DC and Switching Characteristics of HardCopy IV Devices
1–27
Switching Characteristics
Table 1–30. High-Speed I/O Specifications—Preliminary (Part 2 of 2) (Note 1), (2), (3)
Symbol
Conditions
Min Typ Max Unit
Transmitter
Dedicated LVDS—f_HSDR (data rate)
LVDS_E_3R—fHSDRDPA (data rate)
LVDS_E_1R—fHSDRDPA (data rate)
t_{x Jitter}
tDUTY
t t RISE & FALL
TCCS
SERDES factor J = 3 to 10
SERDES factor J = 2, Uses DDR Registers
SERDES factor J = 1, Uses SDR Register
SERDES factor J =4 to 10
Total Jitter for Data Rate, 600Mbps - 1.6Gbps
Total Jitter for Data Rate, < 600Mbps
Tx output clock duty cycle
Dedicated LVDS
LVDS_E_3R
LVDS_E_1R
Dedicated LVDS
LVDS_E_3R/ LVDS_E_1R
150 —
(5) —
(5) —
(5) —
(5) —
—
—
—
—
45
50
—
—
—
—
—
—
—
—
—
—
1250 Mbps
1250 Mbps
717 Mbps
1000 Mbps
200 Mbps
160
ps
0.1
UI
55
%
200
ps
350
ps
500
ps
100
ps
250
ps
Receiver
f_HSDRDPA (data rate)
DPA Mode
DPA run length
SERDES factor J = 3 to 10
—
150 — 1250 Mbps
—
—
(6)
UI
Soft CDR mode
Soft-CDR PPM tolerance
—
—
—
(6)
PPM
Non DPA Mode
Sampling Window
All differential I/O standards
—
—
(6)
ps
Notes to Table 1–30:
(1) Numbers are preliminary pending characterization.
(2) When J = 3 to 10, the SERDES block is used.
(3) When J = 1 or 2, the SERDES block is bypassed.
(4) Clock Boost Factor (Ω) is the ratio between the input data rate to the input clock rate.
(5) The minimum specification is dependent on the clock source (for example, PLL and clock pin) and the clock routing resource (global, regional,
or local) is used.
(6) Pending silicon characterization.
Table 1–31 shows the DPA lock time specifications for HardCopy IV devices.
Table 1–31. DPA Lock Time Specifications—Preliminary (Note 1), (2), (3) (Part 1 of 2)
Standard
Training Pattern
Number of
Data
Transitions
in one
repetition
of training
pattern
Number of
repetition
per 256
data
transition
(4)
Condition
Min
SPI-4
00000000001111111111
2
without DPA PLL
calibration
256 data transitions
128
with DPA PLL
3×256 data transitions + 2×96
calibration
slow clock cycles (5), (6)
Typ Max
——
——
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 4