HC4GX15 Datasheet, PDF (544/668 Pages) Altera Corporation – HardCopy IV Device Handbook

2–86
Figure 2–43. Receiver Core Clocking for Option 2
ASIC Core
Transceiver Block
tx_clkout[0]
TX0 (2 Gbps)
RX0
tx_clkout[1]
tx_clkout[2]
TX1 (2 Gbps)
RX1
TX2 (2 Gbps)
RX2
tx_clkout[3]
TX3 (2 Gbps)
RX3
High speed serial clock generated by the CMU0 PLL
High speed serial clock generated by the CMU1 PLL
Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Description of Transceiver Channel Reconfiguration Modes
CMU1 PLL
CMU0 PLL
Four regular transceiver channels
configured at Basic 2G with
Rate Matching and set up
to switch to different functional modes
with Rate Matching (and different data rates)
HardCopy IV Device Handbook, Volume 3
© June 2009 Altera Corporation