HC4GX15 Datasheet, PDF (91/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 7: External Memory Interfaces in HardCopy IV Devices
7–25
HardCopy IV External Memory Interface Features
DLL
DQS phase-shift circuitry uses a DLL to dynamically measure the clock period
required by the DQS/CQn pin. The DLL, in turn, uses a frequency reference to
generate dynamically controlled signals for the delay chains in each of the DQS and
CQn pins, allowing it to compensate for PVT variations. The DQS delay settings are
Gray-coded to reduce jitter when the DLL updates the settings. The phase-shift
circuitry requires a maximum of 1,280 clock cycles to calculate the correct input clock
period. Data should not be sent during these clock cycles because there is no
guarantee that it will be captured properly. Because the settings from the DLL may
not be stable until this lock period has elapsed, anything using these settings
(including the leveling delay system) may be unstable during this period.
1 You can still use the DQS phase-shift circuitry for any memory interfaces that are less
than 100 MHz. The DQS signal is shifted by 2.5 ns. Even if the DQS signal is not
shifted exactly to the middle of the DQ valid window, the IOE must be able to capture
the data in low frequency applications where a large amount of timing margin is
available.
There are four DLLs in a HardCopy IV device, located in each corner of the device.
These four DLLs can support a maximum of four unique frequencies, with each DLL
running at one frequency. Each DLL can have two outputs with different phase
offsets, allowing one HardCopy IV device to have eight different DLL phase shift
settings. Figure 7–16 shows the DLL and I/O bank locations in HardCopy IV E
devices, from a package-bottom view. Figure 7–17 shows the DLL and I/O bank
locations in HardCopy IV GX devices.
Altera recommends enabling the PLL reconfiguration feature and the DLL phase
offset feature (DLL reconfiguration) for HardCopy IV devices. Because HardCopy IV
devices are mask programmed, they cannot be changed after the silicon is fabricated.
By implementing these two features, you can perform timing adjustments to improve
or resolve timing issues after the silicon is fabricated.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1