HC4GX15 Datasheet, PDF (123/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 8: High-Speed Differential I/O Interfaces and DPA in HardCopy IV Devices
Left and Right PLLs (PLL_Lx and PLL_Rx)
8–13
Figure 8–12. On-Chip Differential Termination
LVDS
Transmitter
Z₀ = 50 Ω
HardCopy IV Differential
Receiver with On-Chip
100 Ω Termination
R_D
Z₀ = 50 Ω
Left and Right PLLs (PLL_Lx and PLL_Rx)
HardCopy IV devices contain a maximum of eight left or right PLLs with up to four
PLLs located on the left side (PLL_L1, PLL_L2, PLL_L3, and PLL_L4) and four on
the right side (PLL_R1, PLL_R2, PLL_R3, and PLL_R4) of the device. The left PLLs
can support high-speed differential I/O banks on the left side; the right PLLs can
support banks only on the right side of the device. The high-speed differential I/O
receiver and transmitter channels use these left and right PLLs to generate the parallel
clocks (rx_outclock and tx_outclock) and high-speed clocks (diffioclk).
Figure 8–1 on page 8–2 and Figure 8–2 on page 8–3 show the locations of the
left/right PLLs for HardCopy IV devices E and HardCopy IV GX, respectively. The
PLL VCO operates at the clock frequency of the data rate. Each left or right PLL offers
a single serial data rate support, but up to two separate serialization or deserialization
factors (from the C0 and C1 of left or right PLL clock outputs), or both. Clock
switchover and dynamic left and right PLL reconfiguration are available in high-
speed differential I/O support mode.
Figure 8–13 shows a simplified diagram of the major components of a HardCopy IV
PLL.
Figure 8–13. HardCopy IV PLL
To DPA block on
Left/Right PLLs
pfdena
Clock inputs
4
from pins
GCLK/RCLK
Cascade input
from adjacent PLL
inclk0
Clock
inclk1
Switchover
Block
Lock
Circuit
locked
÷n
PFD
clkswitch
clkbad0
clkbad1
activeclock
CP
LF
8
VCO
÷2
/2, /4
÷C0
8
÷C1
8
÷C2
÷C3
÷Cn
÷m
no compensation mode
ZDB, External feedback modes
LVDS Compensation mode
Source Synchronous, normal modes
Casade output
to adjacent PLL
GCLKs
RCLKs
External clock
outputs
diffioclk from
Left/Right PLLs
load_en from
Left/Right PLLs
FBOUT
External
memory
interface DLL
FBIN
diffioclk network
GCLK/RCLK network
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1