HC4GX15 Datasheet, PDF (380/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–116
Chapter 1: HardCopy IV GX Transceiver Architecture
Receiver Channel Datapath
Table 1–28. Receiver Phase Compensation FIFO Write Clock Source (Part 2 of 2)
Receiver Phase Compensation FIFO Write Clock
Configuration
×4 bonded channel configuration
×8 bonded channel configuration
Without Byte Serializer
Parallel transmitter PCS clock from the
central clock divider in the CMU0 of the
associated transceiver block
(coreclkout)
Parallel transmitter PCS clock from the
central clock divider in CMU0 of the
master transceiver block (coreclkout
from master transceiver block)
With Byte Serializer
Divide-by-two version of the parallel
transmitter PCS clock from the central
clock divider in CMU0 of the associated
transceiver block (coreclkout)
Divide-by-two version of the parallel
transmitter PCS clock from the central
clock divider in CMU0 of the master
transceiver block (coreclkout from
master transceiver block)
The receiver phase compensation FIFO read clock source varies depending on
whether or not you instantiate the rx_coreclk port in the ALTGX MegaWizard
Plug-In Manager. Table 1–29 shows the receiver phase compensation FIFO read clock
source in different configurations.
Table 1–29. Receiver Phase Compensation FIFO Read Clock Source
Receiver Phase Compensation FIFO Read Clock
Configuration
rx_coreclk Port Not Instantiated
rx_coreclk Port Instantiated (1)
Non-bonded channel
configuration with rate matcher
Core fabric clock driven by the clock
signal on the tx_clkout port
Core fabric clock driven by the clock
signal on the rx_coreclk port
Non-bonded channel
configuration without rate
matcher
Core fabric clock driven by the clock
signal on the rx_clkout port
Core fabric clock driven by the clock
signal on the rx_coreclk port
×4 bonded channel configuration Core fabric clock driven by the clock
signal on the coreclkout port
Core fabric clock driven by the clock
signal on the rx_coreclk port
×8 bonded channel configuration Core fabric clock driven by the clock
signal on the coreclkout port
Core fabric clock driven by the clock
signal on the rx_coreclk port
Note to Table 1–29:
(1) The clock signal driven on the rx_coreclk port must have 0 PPM frequency difference with respect to the receiver phase compensation
FIFO write clock.
Receiver Phase Compensation FIFO Error Flag
An optional rx_phase_comp_fifo_error port is available in all functional modes
to indicate a receiver phase compensation FIFO underrun or overflow condition. The
rx_phase_comp_fifo_error signal is asserted high when the phase
compensation FIFO gets either full or empty. This feature is useful to verify a phase
compensation FIFO underrun or overflow condition as a probable cause of link errors.
Offset Cancellation in the Receiver Buffer and Receiver CDR
As silicon progresses towards smaller process nodes, the performance of circuits at
these smaller nodes depends more on process variations. These process variations
result in analog voltages that can be offset from the required ranges. Offset
cancellation logic corrects these offsets. The receiver buffer and receiver CDR require
offset cancellation.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation