HC4GX15 Datasheet, PDF (294/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–30
Chapter 1: HardCopy IV GX Transceiver Architecture
CMU Channels
Table 1–3. Pins Used as Transmit and Receive Serial Pins (Part 2 of 2)
Pins (1)
When a CMU Channel is
Configured as a Transceiver
Channel
When a CMU Channel
is Configured for
Clock Generation
GXB_TX_[L,R][1,3,5,7]P(3)
Transmit serial output for CMU Not available for use
Channel1
Notes to Table 1–3:
(1) These indexes are for the HardCopy IV GX device with the maximum number of transceiver blocks. For exact
information about how many of these pins are available for a specific device family, refer to the HardCopy IV Device
Family Overview chapter in volume 1 of the HardCopy IV Device Handbook.
(2) Pins 0,2,4,6 are hardwired to CMU channel0 in the corresponding transceiver blocks.
(3) Pins 1,3,5,7 are hardwired to CMU channel1 in the corresponding transceiver blocks.
Interpret the pin column as follows:
For pins REFCLK_[L,R][0,2,4,6]P, GXB_CMURX_[L_R][0,2,4,6], the L, R
indicates the left and right side and the 0, 2, 4, 6 indicates the different pins.
For example, a pin on the left side with index 0 is named: REFCLK_L0P,
GXB_CMURX_L0P.
1 The receiver serial input pins are hardwired to their corresponding CMU channels.
Refer to the notes to Table 1–3.
Serializer and Deserializer
The serializer and deserializer convert the parallel-to-serial and serial-to-parallel data
on the transmitter and receiver side, respectively. The ALTGX MegaWizard Plug-In
Manager provides a new functional mode “Basic (PMA-Direct) mode” (with a none
and ×N option) to configure a transceiver channel to enable the transmitter serializer
and receiver deserializer. To configure a CMU channel as a transceiver channel, you
must use this functional mode.
The input data width options to serializer / from deserializer for a channel configured
in this mode are 8, 10, 16, and 20.
CMU Clock Divider Block
When you configure a CMU channel in Basic (PMA-Direct)×1 mode, this block
divides the high-speed clock from the other CMU channel (used as a clock generation
unit) within the same transceiver block and provides the high-speed serial clock and
low-speed parallel clocks to the transmitter side of the CMU channel. The CMU clock
divider block can divide the high-speed clock by /1, /2, and /4.
Clocks for the Transmitter Serializer
When the CMU channel is configured as a transceiver channel, the clocks for the
transmitter side can be provided by one of these sources:
■ The other CMU channel in the same transceiver block that is configured as a clock
multiplication unit
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation