HC4GX15 Datasheet, PDF (190/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 1: HardCopy IV Design Flow Using the Quartus II Software
Timing Closure and Verification
From the TimeQuest analyzer settings in the Quartus II software, ensure that the
TimeQuest analyzer has the Enable multicorner timing analysis during compilation
check box selected. This setting is necessary to achieve timing closure for the
HardCopy IV ASIC design. By default, the TimeQuest analyzer has this setting
enabled to analyze the design against best-case and worst-case operating conditions
during compilation (Figure 1–14).
To direct the TimeQuest analyzer to remove the common clock path pessimism
during slack computation in the Quartus II software, select the Enable common clock
path pessimism removal option in the TimeQuest Timing Analyzer page
(Figure 1–14).
Figure 1–14. TimeQuest Timing Analyzer Enable Multicorner Timing Analysis During Compilation and Enable Common Clock
Path Pessimism Removal Options
Verification
The Quartus II software uses companion revisions in a single project to promote
conversion of your design from a Stratix IV FPGA to a HardCopy IV ASIC. This
methodology allows you to design with one set of register transfer level (RTL) code to
be used in both the Stratix IV and HardCopy IV designs, guaranteeing functional
equivalency.
HardCopy IV Device Handbook, Volume 2
© January 2010 Altera Corporation