HC4GX15 Datasheet, PDF (283/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Transceiver Port List
Table 1–2. HardCopy IV GX ALTGX Megafunction Ports (Part 12 of 14)
Port Name
tx_forcedispcompliance
tx_forceelecidle
rateswitch
tx_pipemargin
tx_pipedeemph
Input/Output
Description
Input
Force 8B/10B encoder to encode with a
negative running disparity. Functionally
equivalent to the txcompliance signal
defined in PCI Express (PIPE) specification
revision 2.0. Must be asserted high only when
transmitting the first byte of the PIPE
compliance pattern to force the 8B/10B encode
with a negative running disparity as required by
the PIPE protocol.
Input
Force transmitter buffer to PIPE electrical idle
signal levels. Functionally equivalent to the
txelecidle signal defined in the PCI
Express (PIPE) specification revision 2.0.
Input
PIPE rateswitch control.
■ 1’b0—Gen1 (2.5 Gbps)
■ 1’b1—Gen2 (5 Gbps)
Input
Transmitter differential output voltage (V_OD)
level control. This feature is functionally
equivalent to the txmargin signal defined in
the PIPE specification revision 2.0. Available
only in PIPE Gen2 configuration. The width of
this signal is 3 bits per channel and is decoded
as follows:
■ 3’b000—Normal Operating Range
■ 3’b001—Full Swing = 800 – 1200 mV
Low Swing = 400 – 700m V
■ 3’b010—TBD
■ 3’b011—TBD
■ 3’b100—If last value
Full Swing = 200 – 400 mV
■ 3’b101—If last value
Full Swing = 200 – 400 mV
■ 3’b110—If last value
Full Swing = 200 – 400 mV
■ 3’b111—If last value
Full Swing = 200 – 400 mV
Input
Transmitter buffer de-emphasis level control.
This feature is functionally equivalent to the
txdeemph signal defined in the PIPE
specification revision 2.0. Available only in PCI
Express (PIPE) Gen2 configuration.
■ 1’b0: -6 dB de-emphasis
■ 1’b1:-3.5 dB de-emphasis
1–19
Scope
Channel
Channel
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3