HC4GX15 Datasheet, PDF (97/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 7: External Memory Interfaces in HardCopy IV Devices
7–31
HardCopy IV External Memory Interface Features
All DQS and CQn pins referenced to the same DLL can have their input signal phase
shifted by a different degree amount, but all must be referenced at one particular
frequency. For example, you can have a 90° phase shift on DQS1T and a 60° phase shift
on DQS2T referenced from a 200-MHz clock. However, not all phase-shift
combinations are supported. The phase shifts on the DQS pins referenced by the same
DLL must all be a multiple of 22.5° (up to 90°), a multiple of 30° (up to 120°), a
multiple of 36° (up to 144°), or a multiple of 45° (up to 180°).
There are seven different frequency modes for the HardCopy IV DLL, as shown in
Table 7–14. Each frequency mode provides different phase shift selections. In
frequency modes 0, 1, 2, and 3, the 6-bit DQS delay settings vary with PVT to
implement the phase-shift delay. In frequency modes 4, 5, and 6, only 5 bits of the
DQS delay settings vary to implement the phase-shift delay; the most significant bit of
the DQS delay setting is set to 0.
Table 7–14. HardCopy IV DLL Frequency Modes
Frequency Mode
0
1
2
3
4
5
6
DQS Delay Setting Bus
Width
6 bits
6 bits
6 bits
6 bits
5 bits
5 bits
5 bits
Available Phase Shift
22.5°, 45°, 67.5°, 90°
30°, 60°, 90°, 120°
36°, 72°, 108°, 144°
45°, 90°, 135°, 180°
30°, 60°, 90°, 120°
36° 72°, 108°, 144°
45°, 90°, 135°, 180°
Number of Delay
Chains
16
12
10
8
12
10
8
For the 0° shift, the DQS signal bypasses both the DLL and the DQS logic blocks. The
Quartus II software automatically sets DQ input delay chains so that the skew
between the DQ and DQS pin at the DQ IOE registers is negligible when the 0° shift is
implemented. You can feed the DQS delay settings to the DQS logic block and the core
array.
The shifted DQS signal goes to the DQS bus to clock the IOE input registers of the DQ
pins. The signal can also go into the core array for resynchronization if you are not
using the IOE resynchronization registers. The shifted CQn signal can only go to the
negative-edge input register in the DQ IOE and is only used for QDRII+ and QDRII
SRAM interfaces.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1