HC4GX15 Datasheet, PDF (102/668 Pages) Altera Corporation – HardCopy IV Device Handbook

7–36
Chapter 7: External Memory Interfaces in HardCopy IV Devices
HardCopy IV External Memory Interface Features
Figure 7–22. Avoiding Glitch on a Non-Consecutive Read Burst Waveform
DQS
Pos tam ble
Postamble glitch
Pream ble
Postamble Enable
dqsenable
Delayed by
1/2T logic
Leveling Circuitry
DDR3 SDRAM unbuffered modules use a fly-by clock distribution topology for better
signal integrity. This means that the CK/CK# signals arrive at each DDR3 SDRAM
device in the module at different times. The difference in arrival time between the first
DDR3 SDRAM device and the last device on the module can be as long as 1.6 ns.
Figure 7–23 shows the clock topology in DDR3 SDRAM unbuffered modules.
Figure 7–23. DDR3 SDRAM Unbuffered Module Clock Topology
DQS/DQ
DQS/DQ DQS/DQ
DQS/DQ CK/CK# DQS/DQ
DQS/DQ
DQS/DQ
DQS/DQ
HardCopy IV
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation