HC4GX15 Datasheet, PDF (177/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV Design Flow Using the Quartus II Software
1–9
Quartus II Settings for HardCopy IV Devices
In the Quartus II software, be sure the HardCopy IV companion device is selected in
the device selection panel. This ensures that the PLL, other resources used, and the
functions implemented in both the Stratix IV and HardCopy IV designs match. In
addition, it ensures that the design converts successfully.
f For more information about HardCopy IV PLL resources, refer to the Mapping
Stratix IV Device Resources with HardCopy IV Devices chapter.
Add PLL Reconfiguration to Altera IP Blocks
Enable PLL reconfiguration for your design if it uses PLLs. The PLL settings in
HardCopy IV companion devices may require different settings from the Stratix IV
PLLs because of different clock tree lengths and PLL compensations. By enabling PLL
reconfiguration, you can adjust your PLL settings on the HardCopy IV companion
device after the silicon has been fabricated. This allows you to fine tune and further
optimize your system performance.
Use Dedicated Clock Pins
During clock planning, use dedicated clock input pins for high fan-out control signals,
such as asynchronous clears, presets, and clock enables for protocol signals, such as
TRDY and IRDY for PCI Express (PIPE), in global or regional clock networks. These
dedicated routing networks provide predictable delay and minimize skew for high
fan-out signals.
Use dedicated clock pins to drive the PLL reference clock inputs, especially if the
design interfaces with external memories. This minimizes the reference clock input
jitter to the PLLs, providing more timing margin to make the timing closure
successful. For external memory interfaces, Altera recommends using the double date
rate (DDR) register in the I/O element to generate the external memory clocks.
f For information about external memory interfaces, refer to the External Memory
Interfaces in HardCopy IV Devices chapter.
Quartus II Settings for HardCopy IV Devices
The HardCopy IV development flow requires additional Quartus II settings when
compared with a typical FPGA-only design flow. This is because the HardCopy IV
design is implemented in two devices: a Stratix IV prototype and a HardCopy IV
companion device. You must take these settings into consideration when developing
your design.
Limit DSP and RAM to HardCopy Device Resources
To maintain compatibility between the Stratix IV and HardCopy IV devices, your
design must use resources that are common to both families. The Quartus II software
turns on Limit DSP & RAM to HardCopy device resources by default when you
select the Stratix IV device and HardCopy IV companion device in the Quartus II
software. This prevents the Quartus II software from using resources in the Stratix IV
device that are not available in the HardCopy IV device.
Figure 1–3 shows the appropriate setting to select in the Companion device section.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 2