HC4GX15 Datasheet, PDF (540/668 Pages) Altera Corporation – HardCopy IV Device Handbook

2–82
Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Description of Transceiver Channel Reconfiguration Modes
Figure 2–40. Option 1 for Transmitter Core Clocking (Channel and CMU PLL Reconfiguration Mode)
ASIC Core
Transceiver Block
tx_clkout[0]
TX0 (3 Gbps)
RX0
TX1 (3 Gbps)
RX1
TX2 (3 Gbps)
RX2
TX3 (3 Gbps)
RX3
CMU1 PLL
CMU0 PLL
Low-speed parallel clock generated by the TX0 local divider (tx_clkout[0])
High-speed serial clock generated by the CMU0 PLL
HardCopy IV Device Handbook, Volume 3
© June 2009 Altera Corporation