HC4GX15 Datasheet, PDF (658/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–28
Chapter 1: DC and Switching Characteristics of HardCopy IV Devices
Switching Characteristics
Table 1–31. DPA Lock Time Specifications—Preliminary (Note 1), (2), (3) (Part 2 of 2)
Standard
Training Pattern
Number of
Data
Transitions
in one
repetition
of training
pattern
Number of
repetition
per 256
data
transition
(4)
Condition
Min
Parallel
Rapid I/O
00001111
10010000
without DPA PLL
calibration
256 data transitions
2
128
with DPA PLL
3×256 data transitions + 2×96
calibration
slow clock cycles (5), (6)
without DPA PLL
calibration
256 data transitions
4
64
with DPA PLL
3×256 data transitions + 2×96
calibration
slow clock cycles (5), (6)
Misc.
10101010
01010101
without DPA PLL
calibration
256 data transitions
8
32
with DPA PLL
3×256 data transitions + 2×96
calibration
slow clock cycles (5), (6)
without DPA PLL
calibration
256 data transitions
8
32
with DPA PLL
3×256 data transitions + 2×96
calibration
slow clock cycles (5), (6)
Notes to Table 1–31:
(1) The DPA lock time is for one channel.
(2) One data transition is defined as a 0-to-1 or 1-to-0 transition.
(3) The DPA lock time stated in the table applies to both commercial and industrial grade.
(4) This is the number of repetition for the stated training pattern to achieve 256 data transitions.
(5) Slow clock = data rate (MHz)/deserialization factor.
(6) The DPA lock time with DPA PLL Calibration enabled is preliminary.
Typ Max
——
——
——
——
——
——
——
——
Figure 1–4 shows the DPA lock time specifications with DPA PLL calibration enabled.
Figure 1–4. DPA Lock Time Specification with DPA PLL Calibration Enabled
rx_reset
rx_dpa_locked
DPA Lock Time
256 data
transitions
96 slow
clock cycles
256 data
transitions
96 slow
clock cycles
256 data
transitions
External Memory Interface Specifications
Table 1–32 and Table 1–33 list the external memory interface specifications for the
HardCopy IV device family. Use these tables for memory interface timing analysis.
Table 1–32. HardCopy IV Maximum Clock Rate Support for External Memory Interfaces with
Half-Rate Controller—Preliminary (Note 1) (Part 1 of 2)
Memory Standards
MHz
Top and Bottom I/O Banks
Left and Right I/O Banks
DDR3 SDRAM
533 (2)
533 (2)
DDR2 SDRAM
333
333
DDR SDRAM
200
200
QDRII+ SRAM
350
350
HardCopy IV Device Handbook Volume 4
© June 2009 Altera Corporation