HC4GX15 Datasheet, PDF (290/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–26
Chapter 1: HardCopy IV GX Transceiver Architecture
CMU Channels
CMU0 Clock Divider Block
The high-speed clock output from the CMU0 PLL is forwarded to two clock divider
blocks: the CMU0 clock divider block and the transmitter channel local clock divider
block. This clock divider block is used only in bonded channel functional modes. In
all non-bonded functional modes (such as GIGE functional mode), the local clock
divider block divides the high-speed clock to provide clocks for its PCS and PMA
blocks. This section only describes the CMU0 clock divider block.
You can configure the CMU0 clock divider block, shown in Figure 1–10, to select the
high-speed clock output from the CMU0 PLL or CMU1 PLL. The CMU1 PLL is present in
the CMU1 channel.
Figure 1–10. CMU0 Clock Divider Block
PCIE_gen2switch_done
PCIE_gen2switch
CMU0 High-Speed
Clock Output
CMU1 High-Speed
Clock Output
CMU0 Clock Divider Block
/N (1, 2, 4)
PCIE rateswitch
circuit
/S
0
(4, 5, 8, 10)
/2
1
Low-Speed Parallel Clock
for Transmitter Channel PCS
(for Bonded Modes)
coreclkout to core Fabric
(for Bonded Modes)
High-Speed Serial Clock
(for Bonded Modes)
High-Speed Serial Clock Generation
The /N divider receives the high-speed clock output from one of the CMU PLLs and
produces a high-speed serial clock. This high-speed serial clock is used for bonded
functional modes such as Basic ×4, XAUI, and PCI Express (PIPE) ×4 configurations.
In XAUI and Basic ×4 modes, the Quartus II software chooses the path (shown by “1”
in the multiplexer) and provides the high-speed serial clock to all the transmitter
channels within the transceiver block.
In PIPE ×4 mode, the clock path through the PIPE rateswitch circuit block is selected.
This high-speed serial clock is provided to all the transmitter channels.
In PIPE ×8 mode, only the CMU0 clock divider of the master transceiver block
provides the high-speed serial clock to all eight channels.
In PIPE ×1 mode, the CMU0 clock divider does not provide a high-speed serial clock.
Instead, the local clock divider block in the transmitter channel receives the CMU0 PLL
or CMU1 PLL high-speed clock output and generates the high-speed serial clock to its
serializer.
PCIE Rateswitch Circuit
The PCIE rateswitch circuit is enabled only in PIPE ×4 mode. In PIPE ×8 mode, the
PCIE rateswitch circuit of the CMU0 clock divider of the master transceiver block is
active. There are two paths in the PCIE rateswitch circuit. One path divides the /N
output by two. The other path forwards the /N divider output.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation