|
HC4GX15 Datasheet, PDF (602/668 Pages) Altera Corporation – HardCopy IV Device Handbook | |||
|
◁ |
2â144
Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Dynamic Reconfiguration Duration and Core Fabric Resource Utilization
PMA Controls Reconfiguration Duration When Using Method 1
Use the logical_channel_address port in Method 1. The write transaction and
read transaction duration is as follows:
Write Transaction Duration
For writing values to the following PMA controls, the busy signal is asserted for 260
reconfig_clk clock cycles for each of these controls:
â tx_preemp_1t (pre-emphasis control first post-tap)
â tx_vodctrl (voltage output differential)
â rx_eqctrl (equalizer control)
â rx_eqdcgain (equalizer DC gain)
For writing values to the following PMA controls, the busy signal is asserted for 520
reconfig_clk clock cycles for each of these controls:
â tx_preemp_0t (pre-emphasis control pre-tap)
â tx_preemp_2t (pre-emphasis control second post-tap)
Read Transaction Duration
For reading the existing values of the following PMA controls, the busy signal is
asserted for 130 reconfig_clk clock cycles for each of these controls. The
data_valid signal is then asserted once the busy signal goes low.
â tx_preemp_1t_out (pre-emphasis control first post-tap)
â tx_vodctrl_out (voltage output differential)
â rx_eqctrl_out (equalizer control)
â rx_eqdcgain_out (equalizer DC gain)
For reading the existing values of the following PMA controls, the busy signal is
asserted for 260 reconfig_clk clock cycles for each of these controls. The
data_valid signal is then asserted once the busy signal goes low.
â tx_preemp_0t_out (pre-emphasis control pre-tap)
â tx_preemp_2t_out (pre-emphasis control second post-tap)
PMA Controls Reconfiguration Duration When Using Method 2
The logical_channel_address port is not used in Method 2. The write
transaction duration and read transaction duration are as follows:
Write Transaction Duration
For writing values to the following PMA controls, the busy signal is asserted for 260
reconfig_clk clock cycles per channel for each of these controls:
â tx_preemp_1t (pre-emphasis control first post-tap)
â tx_vodctrl (voltage output differential)
â rx_eqctrl (equalizer control)
â rx_eqdcgain (equalizer DC gain)
HardCopy IV Device Handbook, Volume 3
© June 2009 Altera Corporation
|
▷ |