HC4GX15 Datasheet, PDF (95/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 7: External Memory Interfaces in HardCopy IV Devices
7–29
HardCopy IV External Memory Interface Features
Table 7–11. DLL Reference Clock Input for HC4GX15LA and HC4GX25L Devices (Part 2 of 2)
DLL
CLKIN (Top/Bottom)
CLKIN (Left/Right)
DLL4 CLK12P, CLK13P, CLK14P, CLK15P
—
Notes to Table 7–11:
(1) Dedicated clock inputs for DLL1 and DLL2 are not supported in the HC4GX15L devices.
(2) PLL_L1 is not supported in the HC4GX15L devices.
PLL (Top/Bottom) PLL (Left/Right)
PLL_T1
—
Table 7–12. DLL Reference Clock Input for HC4GX25L and HC4GX25F Devices
DLL
CLKIN (Top/Bottom)
DLL1 CLK12P, CLK13P, CLK14P, CLK15P
DLL2 CLK4P, CLK5P, CLK6P, CLK7P
DLL3 CLK4P, CLK5P, CLK6P, CLK7P
DLL4 CLK12P, CLK13P, CLK14P, CLK15P
CLKIN (Left/Right)
CLK0P, CLK1P
CLK0P, CLK1P
CLK11P, CLK10P
CLK11P, CLK10P
PLL (Top/Bottom)
PLL_T1
PLL_B1
PLL_B2
PLL_T2
PLL (Left/Right)
PLL_L1
—
—
PLL_R1
Table 7–13. DLL Reference Clock Input for HC4GX35L and HC4GX35F Devices
DLL
CLKIN (Top/Bottom)
DLL1 CLK12P, CLK13P, CLK14P, CLK15P
DLL2 CLK4P, CLK5P, CLK6P, CLK7P
DLL3 CLK4P, CLK5P, CLK6P, CLK7P
DLL4 CLK12P, CLK13P, CLK14P, CLK15P
CLKIN (Left/Right)
CLK0P, CLK1P, CLK2P, CLK3P
CLK0P, CLK1P, CLK2P, CLK3P
CLK11P, CLK10P, CLK8P, CLK9P
CLK11P, CLK10P, CLK8P, CLK9P
PLL (Top/Bottom) PLL (Left/Right)
PLL_T1
PLL_L1
PLL_B1
PLL_L2
PLL_B2
PLL_R2
PLL_T2
PLL_R1
When you have a dedicated PLL that only generates the DLL input reference clock, set
the PLL mode to No Compensation; otherwise, the Quartus II software changes it
automatically. Because the PLL does not use any other outputs, it does not have to
compensate for any clock paths.
Figure 7–18 shows a block diagram of the DLL. The input reference clock goes into the
DLL to a chain of up to 16 delay elements. The phase comparator compares the signal
coming out of the end of the delay chain block to the input reference clock. The phase
comparator then issues the upndn signal to the Gray-code counter. This signal
increments or decrements a six-bit delay setting (DQS delay settings) that increases or
decreases the delay through the delay element chain to bring the input reference clock
and the signals coming out of the delay element chain in phase.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1