HC4GX15 Datasheet, PDF (537/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 2: HardCopy IV GX Dynamic Reconfiguration
2–79
Description of Transceiver Channel Reconfiguration Modes
1 This logical reference index value is stored as logical tx pll, along with the
other transceiver channel settings in the .mif.
4. Provide the number of input reference clocks available for the CMU PLL in the
How many input clocks? option in the Reconfig Clks screen. The maximum
number of input reference clocks allowed is 10. For more information about this
setting, refer to “General Guidelines for Specifying the Input Reference Clocks” on
page 2–115.
5. Provide the identification of the input reference clock used by the CMU PLL in the
What is the selected input clock source for the Transmitter PLL and Receiver
PLL? option in the Reconfig Clks screen.
6. Set up transceiver and core clocking, which is explained in the following section.
■ Transceiver Clocking Setup
You must set up the transceiver clocking options as part of channel
reconfiguration for functional mode switch over or data rate transition.
Transceiver clocking covers all the clock options you need to set up.
Two CMU PLLs for data rates and functional modes
Input reference clocks for transmit and receive
■ Core Clocking Setup
The transceiver core clocks are the write and read clocks of the Transmit Phase
Compensation FIFO and the Receive Phase Compensation FIFO, respectively.
Core clocking is classified as transmitter core clocking and receiver core
clocking. Table 2–26 explains transmitter core clocking. Similarly, Table 2–27
explains receiver core clocking.
Table 2–26. Transmitter Core Clocking (Part 1 of 2)
Transmitter core clocking refers to the clock that is used to write the parallel data from the core fabric into the Transmit
Phase Compensation FIFO. You can use one of the following clocks to write into the Transmit Phase Compensation FIFO:
■ tx_coreclk—You can use a clock of the same frequency as tx_clkout from the core fabric to provide the write
clock to the Transmit Phase Compensation FIFO. If you use tx_coreclk, it overrides the tx_clkout options in the
ALTGX MegaWizard Plug-In Manager.
■ tx_clkout—The Quartus II software automatically routes tx_clkout to the core fabric and back into the Transmit
Phase Compensation FIFO. There are two options available within the tx_clkout option in the Reconfig 2 screen, as
shown in Figure 2–39.
The following are the two tx_clkout options in the Reconfig 2 screen of the ALTGX MegaWizard Plug-In Manager (1):
Option 1: Share a Single Transmitter Clock between Option 2: Use the Respective Channel Transmitter Core Clocks
Transmitters
© June 2009 Altera Corporation
HardCopy IV Device Handbook, Volume 3