HC4GX15 Datasheet, PDF (43/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 5: Clock Networks and PLLs in HardCopy IV Devices
5–3
PLLs in HardCopy IV Devices
Clock Control Block
HardCopy IV devices also support the same features as the Stratix IV clock control
block, which is available for each GCKL and RCLK network. The clock control block
provides the following features:
■ Clock source selection (dynamic selection for GCLKs)
You can statically or dynamically select the GCLK source. The RCLK source can
only be statically selected. Static selection involves mask programming the clock
multiplexer select inputs. The clock selection is fixed and cannot be changed when
the HardCopy IV device is in user mode. Dynamic selection for the GCLK source
uses internal logic to control the clock multiplexer select inputs when the device is
in user mode. For dynamic clock source selection, you can either select two PLL
outputs (such as CLK0 or CLK1) or a combination of clock pins or PLL outputs.
■ Clock power-down (static or dynamic clock enable or disable)
You can statically or dynamically power-down the GCLK and RCLK networks,
reducing overall power consumption of the device. Unused GCLK and RCLK
networks are powered down through static settings that are automatically
generated by the Quartus II software and that are mask programmed into the
device. The dynamic clock enable or disable feature allows internal logic to
synchronously control power-up or power-down on GCLK and RCLK networks,
including dual-regional clock regions.
PLLs in HardCopy IV Devices
HardCopy IV devices offer up to 12 PLLs that support the same features as the
Stratix IV PLLs. These PLLs provide robust clock management and synthesis for
device clock management, external system clock management, and high-speed I/O
interfaces. The nomenclature for the PLLs follows their geographical location in the
device floorplan. The PLLs that reside on the top and bottom sides of the device are
named PLL_T1, PLL_T2, PLL_B1, and PLL_B2
The PLLs that reside on the left and right sides of the device are named PLL_L1,
PLL_L2, PLL_L3, PLL_L4, PLL_R1, PLL_R2, PLL_R3, and PLL_R4, respectively.
Table 5–2 and Table 5–3 list the number of PLLs available in the HardCopy IV device
family.
Table 5–2. HardCopy IV E Device PLL Availability (Part 1 of 2)
HardCopy IV E
Device
HC4E25WF484N (1)
HC4E25FF484N (1)
HC4E25WF780N
HC4E25FF780N
Stratix IV
Prototype Device
EP4SE230F29 (F780)
EP4SE230F29 (F780)
EP4SE230F29 (F780)
EP4SE360H29 (H780)
EP4SE230F29 (F780)
EP4SE360H29 (H780)
L1 L2 L3 L4 T1
— v — —v
— v — —v
— v — —v
— v — —v
— v — —v
— v — —v
T2 B1 B2 R1 R2
—v — — v
—v — — v
—v — — v
—v — — v
—v — — v
—v — — v
R3 R4
——
——
——
——
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© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1