HC4GX15 Datasheet, PDF (442/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–178
Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
(OIF) CEI PHY Interface Mode Datapath
Figure 1–147 shows the ALTGX megafunction transceiver datapath when configured
in (OIF) CEI PHY interface mode.
Figure 1–147. (OIF) CEI PHY Interface Mode Datapath
Core
Fabric
TX Phase
Compensation
FIFO
wrclk rdclk
tx_coreclk
Core
Fabric-Transmitter
Interface Clock
tx_clkout
RX Phase
Compensation
FIFO
Transmitter Channel PCS
Byte
Serializer
wrclk rdclk
/2
Low-Speed Parallel Clock
Transmitter Channel PMA
Serializer
High-Speed Serial Clock
Local
Clock
Divider
Receiver Channel PCS
Byte
De-
Serializer
Receiver Channel PMA
De-
CDR
Serializer
rx_coreclk
rx_clkout
Core
Fabric-Receiver
Interface Clock
/2
Parallel Recovered Clock
(OIF) CEI PHY Interface Mode Clocking
For improved transmitter jitter performance, the ALTGX MegaWizard Plug-In
Manager provides the Use central clock divider to improve transmitter jitter option.
If you select this option, the high-speed serial clock generated by the CMU0 clock
divider block clocks all four transceiver channels within the same transceiver block.
Otherwise, the high-speed serial clock generated by the local clock divider in each
channel clocks the respective channel.
1 Unlike PCI Express (PIPE) 4, XAUI or Basic ×4 mode, the transmitter PCS is not
bonded in the (OIF) CEI PHY interface mode with the low-jitter option selected.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation