HC4GX15 Datasheet, PDF (536/668 Pages) Altera Corporation – HardCopy IV Device Handbook

2–78
Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Description of Transceiver Channel Reconfiguration Modes
Figure 2–38. Logical Reference Index of CMU PLLs in a Transceiver Block
refclk0
refclk1
156.25 MHz
125 MHz
clock
mux
CMU Channels
6.25 Gbps
CMU0 PLL
clock
mux
2.5 Gbps
CMU1 PLL
full duplex transceiver channel 1
TX CHANNEL 1
Logical
TX PLL
select
LOCAL
DIVIDER
6.25 Gbps
digital+analog logic
clock
mux
RX CHANNEL 1
6.25 Gbps
RX PLL
6.25 Gbps
digital+analog logic
full duplex transceiver channel
2
TX CHANNEL 2
Logical
TX PLL
select
LOCAL
DIVIDER
2.5 Gbps
digital+analog logic
RX CHANNEL 2
clock
mux
2.5 Gbps
RX PLL
2.5 Gbps
digital+analog logic
You can direct the ALTGX_RECONFIG instance to dynamically reconfigure
CMU0 PLL by specifying its logical reference index (the identity of a CMU
PLL). Similarly, you can direct the ALTGX_RECONFIG instance to
dynamically reconfigure CMU1 PLL instead by providing the logical reference
index of CMU1 PLL. The allowed values for the logical reference index are 0
or 1. Similarly, the CMU PLLs in all the transceiver blocks can be assigned a
logical reference index value of 0 or 1.
1 The logical reference index of CMU0 PLL within a transceiver block is
always the complement of the logical reference index of CMU1 PLL within
the same transceiver block.
HardCopy IV Device Handbook, Volume 3
© June 2009 Altera Corporation