HC4GX15 Datasheet, PDF (350/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 1: HardCopy IV GX Transceiver Architecture
Receiver Channel Datapath
The run length violation status signal on the rx_rlv port has lower latency when
compared with the parallel data on the rx_dataout port. The rx_rlv signal in each
channel is clocked by its parallel recovered clock. The core fabric clock might have a
phase difference and/or PPM difference (in asynchronous systems) with respect to
the recovered clock. To ensure that the core fabric clock can latch the rx_rlv signal
reliably, the run length violation circuitry asserts the rx_rlv signal for a minimum of
two recovered clock cycles in single-width modes and a minimum of three recovered
clock cycles in double-width modes. The rx_rlv signal can be asserted longer,
depending on the run length of the received data.
In single-width mode, the run length violation circuit detects up to a run length of 128
(for an 8-bit deserialization factor) or 160 (for a 10-bit deserialization factor). The
settings are in increments of four or five for the 8-bit or 10-bit deserialization factors,
respectively.
In double-width mode, the run length violation circuit maximum run length detection
is 512 (with a run length increment of eight) and 640 (with a run length increment of
10) for the 16-bit and 20-bit deserialization factors, respectively.
Table 1–25 summarizes the detection capabilities of the run length violation circuit.
Table 1–25. Detection Capabilities of the Run Length Violation Circuit
Mode
Single-width mode
Double-width mode
PMA-PCS Interface
Width
8-bit
10-bit
16-bit
20-bit
Run Length Violation Detector Range
Minimum
4
5
8
10
Maximum
128
160
512
640
Receiver Polarity Inversion
The positive and negative signals of a serial differential link are often erroneously
swapped during board layout. Solutions like board re-spin or major updates to the
PLD logic can be expensive. The receiver polarity inversion feature is provided to
correct this situation.
An optional rx_invpolarity port is available in all single-width and double-width
modes except (OIF) CEI PHY and PCI Express (PIPE modes) to dynamically enable
the receiver polarity inversion feature. In single-width modes, a high value on the
rx_invpolarity port inverts the polarity of every bit of the 8-bit or 10-bit input
data word to the word aligner in the receiver datapath. In double-width modes, a
high value on the rx_invpolarity port inverts the polarity of every bit of the 16-bit
or 20-bit input data word to the word aligner in the receiver datapath. Because
inverting the polarity of each bit has the same effect as swapping the positive and
negative signals of the differential link, correct data is seen by the receiver.
rx_invpolarity is a dynamic signal and can cause initial disparity errors in an
8B/10B encoded link. The downstream system must be able to tolerate these disparity
errors.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation